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ADS62P49- 14 bit ADC Output Mismatch for LVDS and LVCMOS

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prem ranjan

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Hi I am using ADS62p49 14 bit adc which supports LVCMOS and LVDS output. I have a low sampling requirement of 30MSPS hence I am using LVCMOS type output in 2's complement form. When I give 10dB sine wave input to the adc, I get a sine wave digital output with dc bias.
Similarly when I am giving no input, I should get lower bits triggered rest all should be LOW. However, bits 3 to bits 14 are fixed at HIGH even with no input meaning the output has been given fixed dc bias of 2^13.

When I give LVDS type and see in ILA, I see proper sine wave with negative as well as positive side. In no input signal case, MSBs are zero and two three bits are triggerred.

Can somebody explain why this difference is being observed in LVCMOS and LVDS mode?
Thanks.
 

You may not be understanding 2s compliment.

11111111111100 in 2's compliment is -4. A small and reasonable DC offset.
 

Yes I understand that but if i read the adc output as unsigned number, the waveform is sine wave but if I read it as signed integer, the output waveform seems to be distorted.
 

Hi,

Please give complete information about input signal (frequency, waveform, amplitude, offset...)
Please give the output values of both modes as Excel (or any other) graph.

Klaus
 

As reported, you get reasonable output in both modes, the only problem is apparently, that setting 2's complement output fails. I suspect a problem in interpretation of SEN pin coding, or a hardware problem. Technically, the difference between both settings is just in inverting MSB, not a big thing.
 

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