FlyingDutch
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Hello in new year 2020 ;-)
After severals experiments with few soft-CPU (Picoblaze, Microblaze, RISC-V) I decided to try implementation of AVR core (ATMega103) from opencores.org - see link:
https://opencores.org/projects/avr_core
I choosed this core because it seems to be complete and have many useful peripherals. The idea is to familiarize with "Vivado HLS" (High Level Synthesis) - I would like to translate into VHDL few libraries for Arduino. Earlier when I have soft-cpu not compatible with AVR and tried to translate Arduino libraries there where parts dependent of some CPU details. With AVR I should be able to translate such libraries without these issues.
I downloaded the project archive form opencores web page and after unpacking archive I realized that there are two versions od ARV-Core: in caralog "trunk" - version 14 (Verilog) and in catalog "web uploads" - version 8 (VHDL). See catalogs with sources on screen:
I made projects in Vivado 2018.2 and added all sources, after that I tried to run synthessis. It turned out that in project are used memory primitives from Artix (RAMB4_S8) - see this documen:
https://www.edaboard.com/newthread.php?do=newthread&f=30
and I head many errors in synthessis. These RAMB4_S8 where used in source files: XDM32Kx8.vhd and XPM8Kx16.vhd. Here are original code in these files:
XDM32Kx8.vhd
XPM8Kx16.vhd
I adde Xilinx IPcore (BRAM Memory - identical as RAMB4_S8) called ABRAMB4_S8 and use it instead RAMB4_S8 in these two source files:
XDM32Kx8.vhd
XPM8Kx16
After that there were no erros during synthesis and implementation, but I had 239 warnings during synthesis and 21 during implementation. Project is configured to "Digilent Cmod A7-35T" board with (Atrtix7 - XC7A35T-1CPG236C ). See links with board description:
https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start?redirect=1id=cmod_a7/cm
https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual
In synthesis raport are many warnings of unused project blocks which are very alarming (I am enclosing only fragment of synthesis raport):
Here is full project made in "Vivado 2018.2":
View attachment AVR_ATMega103_SoftCPU01.zip
Could someone more experienced tell me why there is so much warnings in this design and how they affect working of this core?
In constraints file (XDC) I added only few major ports fron top entity:
Kind Regards
After severals experiments with few soft-CPU (Picoblaze, Microblaze, RISC-V) I decided to try implementation of AVR core (ATMega103) from opencores.org - see link:
https://opencores.org/projects/avr_core
I choosed this core because it seems to be complete and have many useful peripherals. The idea is to familiarize with "Vivado HLS" (High Level Synthesis) - I would like to translate into VHDL few libraries for Arduino. Earlier when I have soft-cpu not compatible with AVR and tried to translate Arduino libraries there where parts dependent of some CPU details. With AVR I should be able to translate such libraries without these issues.
I downloaded the project archive form opencores web page and after unpacking archive I realized that there are two versions od ARV-Core: in caralog "trunk" - version 14 (Verilog) and in catalog "web uploads" - version 8 (VHDL). See catalogs with sources on screen:
I made projects in Vivado 2018.2 and added all sources, after that I tried to run synthessis. It turned out that in project are used memory primitives from Artix (RAMB4_S8) - see this documen:
https://www.edaboard.com/newthread.php?do=newthread&f=30
and I head many errors in synthessis. These RAMB4_S8 where used in source files: XDM32Kx8.vhd and XPM8Kx16.vhd. Here are original code in these files:
XDM32Kx8.vhd
Code:
--************************************************************************************************
-- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM32Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(14 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM32Kx8;
architecture RTL of XDM32Kx8 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_Byte:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEB(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;
XPM8Kx16.vhd
Code:
--************************************************************************************************
-- 8Kx16(16 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM8Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(12 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end XPM8Kx16;
architecture RTL of XPM8Kx16 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
signal gnd : std_logic;
begin
gnd <= '0';
WEBH_Dcd:for i in WEBL'range generate
WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
end generate ;
WEBL_Dcd:for i in WEBH'range generate
WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_ByteLow:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEBL(i),
RST => gnd
);
RAM_ByteHigh:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(15 downto 8),
ADDR => address(8 downto 0),
DI => din(15 downto 8),
EN => ce,
CLK => cp2,
WE => WEBH(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;
I adde Xilinx IPcore (BRAM Memory - identical as RAMB4_S8) called ABRAMB4_S8 and use it instead RAMB4_S8 in these two source files:
XDM32Kx8.vhd
Code:
--************************************************************************************************
-- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM32Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(14 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM32Kx8;
architecture RTL of XDM32Kx8 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
signal BRBusy : std_logic_vector(2**(address'length-9)-1 downto 0);
COMPONENT ABRAMB4_S8
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rsta_busy : OUT STD_LOGIC
);
END COMPONENT;
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_Byte: component ABRAMB4_S8 port map(
clka => cp2,
rsta => gnd,
ena => ce,
wea => WEB(i downto i),
addra => address(8 downto 0),
dina => din(7 downto 0),
douta => RAMBlDOut(i)(7 downto 0),
rsta_busy => BRBusy(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;
XPM8Kx16
Code:
--************************************************************************************************
-- 8Kx16(16 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM8Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(12 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end XPM8Kx16;
architecture RTL of XPM8Kx16 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
signal gnd : std_logic;
signal BRBusy : std_logic_vector(2**(address'length-9)-1 downto 0);
signal BRBusy1 : std_logic_vector(2**(address'length-9)-1 downto 0);
COMPONENT ABRAMB4_S8
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rsta_busy : OUT STD_LOGIC
);
END COMPONENT;
begin
gnd <= '0';
WEBH_Dcd:for i in WEBL'range generate
WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
end generate ;
WEBL_Dcd:for i in WEBH'range generate
WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_ByteLow: component ABRAMB4_S8 port map(
douta => RAMBlDOut(i)(7 downto 0),
addra => address(8 downto 0),
dina => din(7 downto 0),
ena => ce,
clka => cp2,
wea => WEBL(i downto i),
rsta => gnd,
rsta_busy => BRBusy(i)
);
RAM_ByteHigh: component ABRAMB4_S8 port map(
douta => RAMBlDOut(i)(15 downto 8),
addra => address(8 downto 0),
dina => din(15 downto 8),
ena => ce,
clka => cp2,
wea => WEBH(i downto i),
rsta => gnd,
rsta_busy => BRBusy1(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;
After that there were no erros during synthesis and implementation, but I had 239 warnings during synthesis and 21 during implementation. Project is configured to "Digilent Cmod A7-35T" board with (Atrtix7 - XC7A35T-1CPG236C ). See links with board description:
https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start?redirect=1id=cmod_a7/cm
https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual
In synthesis raport are many warnings of unused project blocks which are very alarming (I am enclosing only fragment of synthesis raport):
Code:
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd:28]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:576]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:630]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:642]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:654]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:666]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:678]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:690]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:702]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:714]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:726]
WARNING: [Synth 8-6014] Unused sequential element LatchWrData_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:448]
WARNING: [Synth 8-6014] Unused sequential element EEWrStart_Int_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:460]
WARNING: [Synth 8-6014] Unused sequential element EERdStart_Int_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:468]
WARNING: [Synth 8-6014] Unused sequential element EEPROMWr_St_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:461]
WARNING: [Synth 8-6014] Unused sequential element FuseWr_St_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:613]
WARNING: [Synth 8-6014] Unused sequential element LockWr_St_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:614]
WARNING: [Synth 8-6014] Unused sequential element LoadNOP_St_reg was removed. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:617]
WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'PCRShIn_reg' in module 'OCDProgTCK' in the same process may cause logic issues.
Please split the sync and async parts into different processes [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:272]
WARNING: [Synth 8-3848] Net EEWrStart in module/entity OCDProgTCK does not have driver. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:37]
WARNING: [Synth 8-3848] Net EERdStart in module/entity OCDProgTCK does not have driver. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'OCDProgTCK' (16#1) [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:45]
INFO: [Synth 8-638] synthesizing module 'OCDProgcp2' [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:51]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:131]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:143]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:189]
INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:292]
Here is full project made in "Vivado 2018.2":
View attachment AVR_ATMega103_SoftCPU01.zip
Could someone more experienced tell me why there is so much warnings in this design and how they affect working of this core?
In constraints file (XDC) I added only few major ports fron top entity:
Code:
## Clock signal 12 MHz
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk}];
## Buttons
set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { nrst }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
## GPIO Pins
## Pins 15 and 16 should remain commented if using them as analog inputs
set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { rxd }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { txd }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
Kind Regards
Last edited: