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  1. #1
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    AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Hello in new year 2020

    After severals experiments with few soft-CPU (Picoblaze, Microblaze, RISC-V) I decided to try implementation of AVR core (ATMega103) from opencores.org - see link:

    https://opencores.org/projects/avr_core

    I choosed this core because it seems to be complete and have many useful peripherals. The idea is to familiarize with "Vivado HLS" (High Level Synthesis) - I would like to translate into VHDL few libraries for Arduino. Earlier when I have soft-cpu not compatible with AVR and tried to translate Arduino libraries there where parts dependent of some CPU details. With AVR I should be able to translate such libraries without these issues.

    I downloaded the project archive form opencores web page and after unpacking archive I realized that there are two versions od ARV-Core: in caralog "trunk" - version 14 (Verilog) and in catalog "web uploads" - version 8 (VHDL). See catalogs with sources on screen:

    Click image for larger version. 

Name:	Catalogs01.png 
Views:	4 
Size:	122.2 KB 
ID:	157208

    I made projects in Vivado 2018.2 and added all sources, after that I tried to run synthessis. It turned out that in project are used memory primitives from Artix (RAMB4_S8) - see this documen:

    https://www.edaboard.com/newthread.p...newthread&f=30

    and I head many errors in synthessis. These RAMB4_S8 where used in source files: XDM32Kx8.vhd and XPM8Kx16.vhd. Here are original code in these files:

    XDM32Kx8.vhd
    Code:
    --************************************************************************************************
    -- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
    -- Version 0.1
    -- Designed by Ruslan Lepetenok 
    -- Modified 29.10.2005
    --************************************************************************************************
    
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    
    -- For Synplicity Synplify
    --library virtexe;
    --use	virtexe.components.all; 
    
    -- Aldec
    library	unisim;
    use unisim.vcomponents.all;
    
    entity XDM32Kx8 is port(
    	                            cp2       : in  std_logic;
    					    ce        : in  std_logic; 
    	                            address   : in  std_logic_vector(14 downto 0); 
    					    din       : in  std_logic_vector(7 downto 0);		                
    					    dout      : out std_logic_vector(7 downto 0);
    					    we        : in  std_logic
    					   );
    end XDM32Kx8;
    
    architecture RTL of XDM32Kx8 is
    
    type   RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of  std_logic_vector(dout'range);
    signal RAMBlDOut     : RAMBlDOut_Type;
    
    signal WEB      : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal cp2n     : std_logic;
    signal gnd      : std_logic;
    
    begin
    
    gnd  <= '0';	
    
    WEB_Dcd:for i in WEB'range generate 
     WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
    end generate ;
    
    
    RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
    
    RAM_Byte:component RAMB4_S8 port map(
                                          DO   => RAMBlDOut(i)(7 downto 0),
                                          ADDR => address(8 downto 0),
                                          DI   => din(7 downto 0),
                                          EN   => ce,
                                          CLK  => cp2,
                                          WE   => WEB(i),
                                          RST  => gnd
                                          );
    								  
    end generate;
    
    -- Output data mux
    dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
    
    end RTL;
    XPM8Kx16.vhd
    Code:
    --************************************************************************************************
    -- 8Kx16(16 KB) PM RAM for AVR Core(Xilinx)
    -- Version 0.1
    -- Designed by Ruslan Lepetenok 
    -- Modified 29.10.2005
    --************************************************************************************************
    
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    
    -- For Synplicity Synplify
    --library virtexe;
    --use	virtexe.components.all; 
    
    -- Aldec
    library	unisim;
    use unisim.vcomponents.all;
    
    entity XPM8Kx16 is port(
    	                          cp2     : in  std_logic;
    					  ce      : in  std_logic; 
    	                          address : in  std_logic_vector(12 downto 0); 
    					  din     : in  std_logic_vector(15 downto 0);		                
    					  dout    : out std_logic_vector(15 downto 0);
    					  weh     : in  std_logic;
    					  wel     : in  std_logic
    					  );
    end XPM8Kx16;
    
    architecture RTL of XPM8Kx16 is
    
    type   RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of  std_logic_vector(dout'range);
    signal RAMBlDOut     : RAMBlDOut_Type;
    
    signal WEBL     : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal WEBH     : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal gnd      : std_logic;
    
    begin
    
    gnd <= '0';	
    
    WEBH_Dcd:for i in WEBL'range generate 
     WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
    end generate ;
    
    WEBL_Dcd:for i in WEBH'range generate 
     WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
    end generate ;
    
    
    RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
    
    RAM_ByteLow:component RAMB4_S8 port map(
                                          DO   => RAMBlDOut(i)(7 downto 0),
                                          ADDR => address(8 downto 0),
                                          DI   => din(7 downto 0),
                                          EN   => ce,
                                          CLK  => cp2,
                                          WE   => WEBL(i),
                                          RST  => gnd
                                          );
    
    RAM_ByteHigh:component RAMB4_S8 port map(
                                          DO   => RAMBlDOut(i)(15 downto 8),
                                          ADDR => address(8 downto 0),
                                          DI   => din(15 downto 8),
                                          EN   => ce,
                                          CLK  => cp2,
                                          WE   => WEBH(i),
                                          RST  => gnd
                                          );
    									  
    end generate;
    
    -- Output data mux
    dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
    
    
    end RTL;
    I adde Xilinx IPcore (BRAM Memory - identical as RAMB4_S8) called ABRAMB4_S8 and use it instead RAMB4_S8 in these two source files:

    XDM32Kx8.vhd
    Code:
    --************************************************************************************************
    -- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
    -- Version 0.1
    -- Designed by Ruslan Lepetenok 
    -- Modified 29.10.2005
    --************************************************************************************************
    
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    
    -- For Synplicity Synplify
    --library virtexe;
    --use	virtexe.components.all; 
    
    -- Aldec
    library	unisim;
    use unisim.vcomponents.all;
    
    entity XDM32Kx8 is port(
    	                    cp2       : in  std_logic;
    					    ce        : in  std_logic; 
    	                    address   : in  std_logic_vector(14 downto 0); 
    					    din       : in  std_logic_vector(7 downto 0);		                
    					    dout      : out std_logic_vector(7 downto 0);
    					    we        : in  std_logic
    					   );
    end XDM32Kx8;
    
    architecture RTL of XDM32Kx8 is
    
    type   RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of  std_logic_vector(dout'range);
    signal RAMBlDOut     : RAMBlDOut_Type;
    
    signal WEB      : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal cp2n     : std_logic;
    signal gnd      : std_logic;
    signal BRBusy   : std_logic_vector(2**(address'length-9)-1 downto 0);
    
    COMPONENT ABRAMB4_S8
      PORT (
        clka : IN STD_LOGIC;
        rsta : IN STD_LOGIC;
        ena : IN STD_LOGIC;
        wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        rsta_busy : OUT STD_LOGIC
      );
    END COMPONENT;
    
    begin
    
    gnd  <= '0';	
    
    WEB_Dcd:for i in WEB'range generate 
     WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
    end generate ;
    
    
    RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
                                                                             
    RAM_Byte: component ABRAMB4_S8 port map(
                                          clka => cp2,
                                          rsta  => gnd,
                                          ena   => ce,
                                          wea   => WEB(i downto i),
                                          addra => address(8 downto 0),
                                          dina   => din(7 downto 0),
                                          douta   => RAMBlDOut(i)(7 downto 0),
                                          rsta_busy => BRBusy(i)
                                          );                                                                            
    								  
    end generate;
    
    -- Output data mux
    dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
    
    end RTL;
    XPM8Kx16
    Code:
    --************************************************************************************************
    -- 8Kx16(16 KB) PM RAM for AVR Core(Xilinx)
    -- Version 0.1
    -- Designed by Ruslan Lepetenok 
    -- Modified 29.10.2005
    --************************************************************************************************
    
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    
    -- For Synplicity Synplify
    --library virtexe;
    --use	virtexe.components.all; 
    
    -- Aldec
    library	unisim;
    use unisim.vcomponents.all;
    
    entity XPM8Kx16 is port(
    	                  cp2     : in  std_logic;
    					  ce      : in  std_logic; 
    	                  address : in  std_logic_vector(12 downto 0); 
    					  din     : in  std_logic_vector(15 downto 0);		                
    					  dout    : out std_logic_vector(15 downto 0);
    					  weh     : in  std_logic;
    					  wel     : in  std_logic
    					  );
    end XPM8Kx16;
    
    architecture RTL of XPM8Kx16 is
    
    type   RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of  std_logic_vector(dout'range);
    signal RAMBlDOut     : RAMBlDOut_Type;
    
    signal WEBL     : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal WEBH     : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal gnd      : std_logic;
    signal BRBusy   : std_logic_vector(2**(address'length-9)-1 downto 0);
    signal BRBusy1  : std_logic_vector(2**(address'length-9)-1 downto 0);
    
    
    
    COMPONENT ABRAMB4_S8
      PORT (
        clka : IN STD_LOGIC;
        rsta : IN STD_LOGIC;
        ena : IN STD_LOGIC;
        wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        rsta_busy : OUT STD_LOGIC
      );
    END COMPONENT;
    
    begin
    
    gnd <= '0';	
    
    WEBH_Dcd:for i in WEBL'range generate 
     WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
    end generate ;
    
    WEBL_Dcd:for i in WEBH'range generate 
     WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
    end generate ;
    
    RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
    
    RAM_ByteLow: component ABRAMB4_S8 port map(
                                          douta   => RAMBlDOut(i)(7 downto 0),
                                          addra => address(8 downto 0),
                                          dina   => din(7 downto 0),
                                          ena   => ce,
                                          clka  => cp2,
                                          wea   => WEBL(i downto i),
                                          rsta  => gnd,
                                          rsta_busy => BRBusy(i)
                                          );
    
    RAM_ByteHigh: component ABRAMB4_S8 port map(
                                          douta   => RAMBlDOut(i)(15 downto 8),
                                          addra => address(8 downto 0),
                                          dina   => din(15 downto 8),
                                          ena   => ce,
                                          clka  => cp2,
                                          wea   => WEBH(i downto i),
                                          rsta  => gnd,
                                          rsta_busy => BRBusy1(i)                                      
                                          );
    									  
    end generate;
    
    -- Output data mux
    dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
    
    
    end RTL;
    After that there were no erros during synthesis and implementation, but I had 239 warnings during synthesis and 21 during implementation. Project is configured to "Digilent Cmod A7-35T" board with (Atrtix7 - XC7A35T-1CPG236C ). See links with board description:

    https://reference.digilentinc.com/re...1id=cmod_a7/cm

    https://reference.digilentinc.com/re...ference-manual

    In synthesis raport are many warnings of unused project blocks which are very alarming (I am enclosing only fragment of synthesis raport):

    Code:
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd:28]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:576]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:630]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:642]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:654]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:666]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:678]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:690]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:702]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:714]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:726]
    WARNING: [Synth 8-6014] Unused sequential element LatchWrData_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:448]
    WARNING: [Synth 8-6014] Unused sequential element EEWrStart_Int_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:460]
    WARNING: [Synth 8-6014] Unused sequential element EERdStart_Int_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:468]
    WARNING: [Synth 8-6014] Unused sequential element EEPROMWr_St_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:461]
    WARNING: [Synth 8-6014] Unused sequential element FuseWr_St_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:613]
    WARNING: [Synth 8-6014] Unused sequential element LockWr_St_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:614]
    WARNING: [Synth 8-6014] Unused sequential element LoadNOP_St_reg was removed.  [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:617]
    WARNING: [Synth 8-6426] Mix of Sync and Async assignments to register 'PCRShIn_reg' in module 'OCDProgTCK' in the same process may cause logic issues. 
     Please split the sync and async parts into different processes [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:272]
    WARNING: [Synth 8-3848] Net EEWrStart in module/entity OCDProgTCK does not have driver. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:37]
    WARNING: [Synth 8-3848] Net EERdStart in module/entity OCDProgTCK does not have driver. [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:38]
    INFO: [Synth 8-256] done synthesizing module 'OCDProgTCK' (16#1) [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgTCK.vhd:45]
    INFO: [Synth 8-638] synthesizing module 'OCDProgcp2' [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:51]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:131]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:143]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:189]
    INFO: [Synth 8-226] default block is never used [C:/Users/mgabr/Vivado/AVR_ATMega103_SoftCPU01/AVR_ATMega103_SoftCPU01.srcs/sources_1/imports/AVR_ATMega103_SoftCPU01/JTAG_OCD_Prg/OCDProgcp2.vhd:292]
    Here is full project made in "Vivado 2018.2":

    AVR_ATMega103_SoftCPU01.zip

    Could someone more experienced tell me why there is so much warnings in this design and how they affect working of this core?

    In constraints file (XDC) I added only few major ports fron top entity:

    Code:
    ## Clock signal 12 MHz
    set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
    create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk}];
    
    ## Buttons
    set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { nrst }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
    
    ## GPIO Pins
    ## Pins 15 and 16 should remain commented if using them as analog inputs
    set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { rxd }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
    set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { txd }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
    Kind Regards
    Last edited by FlyingDutch; 4th January 2020 at 18:29.

  2. #2
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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Did you have a specific question?



  3. #3
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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    This is second part of my post:

    I am a bit confused because this is soft-core with status stable and was checked earlier. Maybe reason of such many warnings is caused that it is old design (as far as I can see the project was made with Xilinx ISE10), The project also had some parts based on Xilinx Virtex FPGA and is hardware dependend.

    See screen with project summary (warnings):

    Click image for larger version. 

Name:	AVRWarnings_.png 
Views:	5 
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    There are more issues related to adding ports from top entity to "constraints file" -xdc which gives erros during placement phase of implementation, but I describe then in second post.

    Regards

    - - - Updated - - -

    Quote Originally Posted by TrickyDicky View Post
    Did you have a specific question?
    This is my question: Could someone more experienced tell me why there is so much warnings in this design and how they affect proper working of this core in real FPGA circuit?

    Regards

    Link with Artix primitives (second of first post) should be:

    https://www.xilinx.com/support/docum...virtex_hdl.pdf
    Last edited by FlyingDutch; 4th January 2020 at 19:15.



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    The warnings you posted are just that: warnings. They relate to code you havent posted.

    "default block is never used"
    This usually means there is an others assignment in a case statement or an else statement that cannot be reached because all cases are already covered explicitly. This is probably a good thing.

    "Unused sequential element XXXX was removed."
    This means there is a register that has no effect on any observable outputs. hence it is removed from the design.

    "Net XXX does not have driver."
    Means XXX is never assigned a value or initialised with a value.

    "Mix of Sync and Async assignments to register"
    This is a bit weird. This shouldnt really be possible in VHDL.

    Warnings are pretty normal in FPGA projects. You can try and clear them but you likely never will, espeically if you use any IP cores. If the design works as expected in your testbenches (that are good quality self checking testbenches) then it is likely to work on the board. You must pay attention to "critical warnings" though.

    On a side note - stuff from opencores are basically just hobby projects. Ive never been impressed with any code there and dont expect any support.


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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Hello,

    this is next part of my post, it is related to errors in implementation phase (placement), after adding to constraint file all ports from top entity.

    First - this is top entity of project (only ports):

    Code:
    entity top_avr_core_v8 is port(
                                   nrst   : in    std_logic;
                                   clk    : in    std_logic;
                                   porta  : inout std_logic_vector(7 downto 0);
                                   portb  : inout std_logic_vector(7 downto 0);
    	                       -- UART 
    	                        rxd    : in    std_logic;
    	                        txd    : out   std_logic;
    				-- External interrupts
    				INTx   : in    std_logic_vector(7 downto 0); 
    				 -- JTAG related signals
    	                       TMS    : in    std_logic;
                                   TCK	  : in    std_logic;
                                   TDI    : in    std_logic;
                                   TDO    : out   std_logic;
    	                       TRSTn  : in    std_logic -- Optional JTAG inpu
                                );
    end top_avr_core_v8;
    Here is Cmod7_Master.xdc file (from Digilent page) for used FPGA board:

    Code:
    ## This file is a general .xdc for the CmodA7 rev. B
    ## To use it in a project:
    ## - uncomment the lines corresponding to used pins
    ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
    
    ## Clock signal 12 MHz
    #set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
    #create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
    
    
    ## LEDs
    #set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
    #set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
    
    #set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b
    #set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
    #set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
    
    
    ## Buttons
    #set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
    #set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
    
    
    ## Pmod Header JA
    #set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1]
    #set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2]
    #set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
    #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
    #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
    #set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8]
    #set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9]
    #set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10]
    
    
    ## Analog XADC Pins
    ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
    #set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
    #set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
    #set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
    #set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
    
    
    ## GPIO Pins
    ## Pins 15 and 16 should remain commented if using them as analog inputs
    #set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { pio[01] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
    #set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { pio[02] }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
    #set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { pio[03] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
    #set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { pio[04] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
    #set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { pio[05] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
    #set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { pio[06] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
    #set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { pio[07] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
    #set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { pio[08] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
    #set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { pio[09] }]; #IO_L6P_T0_16 Sch=pio[09]
    #set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { pio[10] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
    #set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { pio[11] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
    #set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { pio[12] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
    #set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { pio[13] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
    #set_property -dict { PACKAGE_PIN L2    IOSTANDARD LVCMOS33 } [get_ports { pio[14] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
    #set_property -dict { PACKAGE_PIN M1    IOSTANDARD LVCMOS33 } [get_ports { pio[17] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
    #set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { pio[18] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
    #set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { pio[19] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
    #set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { pio[20] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
    #set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { pio[21] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
    #set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { pio[22] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
    #set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { pio[23] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
    #set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { pio[26] }]; #IO_L2P_T0_34 Sch=pio[26]
    #set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { pio[27] }]; #IO_L2N_T0_34 Sch=pio[27]
    #set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { pio[28] }]; #IO_L1P_T0_34 Sch=pio[28]
    #set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { pio[29] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
    #set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { pio[30] }]; #IO_L1N_T0_34 Sch=pio[30]
    #set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { pio[31] }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
    #set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { pio[32] }]; #IO_L5N_T0_34 Sch=pio[32]
    #set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { pio[33] }]; #IO_L5P_T0_34 Sch=pio[33]
    #set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { pio[34] }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
    #set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { pio[35] }]; #IO_L6P_T0_34 Sch=pio[35]
    #set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { pio[36] }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
    #set_property -dict { PACKAGE_PIN V4    IOSTANDARD LVCMOS33 } [get_ports { pio[37] }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
    #set_property -dict { PACKAGE_PIN U4    IOSTANDARD LVCMOS33 } [get_ports { pio[38] }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
    #set_property -dict { PACKAGE_PIN V5    IOSTANDARD LVCMOS33 } [get_ports { pio[39] }]; #IO_L16N_T2_34 Sch=pio[39]
    #set_property -dict { PACKAGE_PIN W4    IOSTANDARD LVCMOS33 } [get_ports { pio[40] }]; #IO_L12N_T1_MRCC_34 Sch=pio[40]
    #set_property -dict { PACKAGE_PIN U5    IOSTANDARD LVCMOS33 } [get_ports { pio[41] }]; #IO_L16P_T2_34 Sch=pio[41]
    #set_property -dict { PACKAGE_PIN U2    IOSTANDARD LVCMOS33 } [get_ports { pio[42] }]; #IO_L9N_T1_DQS_34 Sch=pio[42]
    #set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33 } [get_ports { pio[43] }]; #IO_L13N_T2_MRCC_34 Sch=pio[43]
    #set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { pio[44] }]; #IO_L9P_T1_DQS_34 Sch=pio[44]
    #set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33 } [get_ports { pio[45] }]; #IO_L19P_T3_34 Sch=pio[45]
    #set_property -dict { PACKAGE_PIN W7    IOSTANDARD LVCMOS33 } [get_ports { pio[46] }]; #IO_L13P_T2_MRCC_34 Sch=pio[46]
    #set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS33 } [get_ports { pio[47] }]; #IO_L14P_T2_SRCC_34 Sch=pio[47]
    #set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports { pio[48] }]; #IO_L14N_T2_SRCC_34 Sch=pio[48]
    
    
    ## UART
    #set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
    #set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in  }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
    
    
    ## Crypto 1 Wire Interface
    #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
    
    
    ## QSPI
    #set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs    }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
    #set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
    #set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
    #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
    #set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
    
    
    ## Cellular RAM
    #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0]  }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
    #set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1]  }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
    #set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2]  }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
    #set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3]  }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
    #set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4]  }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
    #set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5]  }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
    #set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6]  }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
    #set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7]  }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
    #set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8]  }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
    #set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9]  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
    #set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
    #set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
    #set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
    #set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
    #set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
    #set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
    #set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
    #set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
    #set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
    #set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[0]   }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
    #set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[1]   }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
    #set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[2]   }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
    #set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[3]   }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
    #set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { MemDB[4]   }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
    #set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[5]   }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
    #set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[6]   }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
    #set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[7]   }]; #IO_25_14 Sch=sram-dq[7]
    #set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { RamOEn     }]; #IO_L10P_T1_D14_14 Sch=sram-oe
    #set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { RamWEn     }]; #IO_L10N_T1_D15_14 Sch=sram-we
    #set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports { RamCEn     }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce
    And here is my project constraint file top_avr_core_v8.xdc:
    Code:
    ## Clock signal 12 MHz
    set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
    create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk}];
    
    ## Buttons
    set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { nrst }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
    
    ## GPIO Pins
    ## Pins 15 and 16 should remain commented if using them as analog inputs
    set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { rxd }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
    set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { txd }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
    
    set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { porta[7] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
    set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { porta[6] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
    set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { porta[5] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
    set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { porta[4] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
    set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { porta[3] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
    set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { porta[2] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
    set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { porta[1] }]; #IO_L6P_T0_16 Sch=pio[09]
    set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { porta[0] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
    
    set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { portb[7] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
    set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { portb[6] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
    set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { portb[5] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
    set_property -dict { PACKAGE_PIN L2    IOSTANDARD LVCMOS33 } [get_ports { portb[4] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
    set_property -dict { PACKAGE_PIN M1    IOSTANDARD LVCMOS33 } [get_ports { portb[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
    set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { portb[2] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
    set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { portb[1] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
    set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { portb[0] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
    
    set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { INTx[7] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
    set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { INTx[6] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
    set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { INTx[5] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
    set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { INTx[4] }]; #IO_L2P_T0_34 Sch=pio[26]
    set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { INTx[3] }]; #IO_L2N_T0_34 Sch=pio[27]
    set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { INTx[2] }]; #IO_L1P_T0_34 Sch=pio[28]
    set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { INTx[1] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
    set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { INTx[0] }]; #IO_L1N_T0_34 Sch=pio[30]
    
    set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { TMS }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
    set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { TCK }]; #IO_L5N_T0_34 Sch=pio[32]
    set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { TDI }]; #IO_L5P_T0_34 Sch=pio[33]
    set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { TDO }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
    set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { TRSTn }]; #IO_L6P_T0_34 Sch=pio[35]
    After synthesis and implementation I have now 3 erros in implementation phase (placement) - see screen:

    Click image for larger version. 

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    Here are these errors as text:
    Code:
    Implementation
    Place Design
    
    [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK_IBUF] >
    
    	TCK_IBUF_inst (IBUF.O) is locked to IOB_X1Y39
    	 and TCK_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
    
    [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
    Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
    
    [Common 17-69] Command failed: Placer could not place all instances
    I don't fully understand these errors, could someone to get rid of these errors?

    Regards
    Last edited by FlyingDutch; 5th January 2020 at 11:16.



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Hello,

    I added the directive: "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK_IBUF]" from hint related to placement error and now I only have warnings during implementation phase, but I am afraid that this weak routing of clock might affect proper working of JTAG programmmer.

    If someone is able to give better solution please do it - I will be grateful

    Now constraint file looks like this:
    Code:
    ## Clock signal 12 MHz
    set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
    create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk}];
    
    ## Buttons
    set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { nrst }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
    
    ## GPIO Pins
    ## Pins 15 and 16 should remain commented if using them as analog inputs
    set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { rxd }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
    set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { txd }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
    
    set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { porta[7] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
    set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { porta[6] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
    set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { porta[5] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
    set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { porta[4] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
    set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { porta[3] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
    set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { porta[2] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
    set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { porta[1] }]; #IO_L6P_T0_16 Sch=pio[09]
    set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { porta[0] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
    
    set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { portb[7] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
    set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { portb[6] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
    set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { portb[5] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
    set_property -dict { PACKAGE_PIN L2    IOSTANDARD LVCMOS33 } [get_ports { portb[4] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
    set_property -dict { PACKAGE_PIN M1    IOSTANDARD LVCMOS33 } [get_ports { portb[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
    set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { portb[2] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
    set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { portb[1] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
    set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { portb[0] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
    
    set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { INTx[7] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
    set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { INTx[6] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
    set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { INTx[5] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
    set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { INTx[4] }]; #IO_L2P_T0_34 Sch=pio[26]
    set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { INTx[3] }]; #IO_L2N_T0_34 Sch=pio[27]
    set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { INTx[2] }]; #IO_L1P_T0_34 Sch=pio[28]
    set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { INTx[1] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
    set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { INTx[0] }]; #IO_L1N_T0_34 Sch=pio[30]
    
    set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { TMS }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK_IBUF]
    set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { TCK }]; #IO_L5N_T0_34 Sch=pio[32]
    set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { TDI }]; #IO_L5P_T0_34 Sch=pio[33]
    set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { TDO }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
    set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { TRSTn }]; #IO_L6P_T0_34 Sch=pio[35]
    Then theoretically this is working Vivado(2018.2) project of "AVR Core" for Artix7. Near days I will try to check proper working of this project on CmodA7 FPGA board, then I write few words about it.

    Regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    I added the directive: "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK_IBUF]" from hint related to placement error and now I only have warnings during implementation phase, but I am afraid that this weak routing of clock might affect proper working of JTAG programmmer.
    That's the only work around if you don't have a clock capable pin. If you have one try moving the signal to it.

    Having set it to FALSE, did your design pass timing? Because that is the penalty here, longer path delays.

    Did you get a timing clean netlist? If yes, just download that bitfile into your FPGA and see if stuff works.
    FPGA enthusiast!


    1 members found this post helpful.

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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Quote Originally Posted by dpaul View Post
    That's the only work around if you don't have a clock capable pin. If you have one try moving the signal to it.

    Having set it to FALSE, did your design pass timing? Because that is the penalty here, longer path delays.

    Did you get a timing clean netlist? If yes, just download that bitfile into your FPGA and see if stuff works.
    Hello,

    I am aware that longer delays can occure. I just wanna to try it on FPGA, but today I haven't JTAG programmer for AVR (I will have access to programer tomorrow).
    If I will try the project on FPGA, then I desribe few words if it is working. The lucky is that for JTAG programmer I can set low clock frequency ;)

    Regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    The pin describe for use by jtag is not a clock capable pin. Depending on the pin location and the global buffer used this can result in a significant clock insertion delay. The timing reports will tell you what the insertion delay for the clock is.

    There are a bunch of the MRCC pins that are currently used by porta and portb where you could move jtag and put TCK on a clock capable pin.


    1 members found this post helpful.

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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Quote Originally Posted by ads-ee View Post
    The pin describe for use by jtag is not a clock capable pin. Depending on the pin location and the global buffer used this can result in a significant clock insertion delay. The timing reports will tell you what the insertion delay for the clock is.

    There are a bunch of the MRCC pins that are currently used by porta and portb where you could move jtag and put TCK on a clock capable pin.
    Hello,

    thanks for hint, i will try do it.

    Regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Quote Originally Posted by ads-ee View Post
    The pin describe for use by jtag is not a clock capable pin. Depending on the pin location and the global buffer used this can result in a significant clock insertion delay. The timing reports will tell you what the insertion delay for the clock is.

    There are a bunch of the MRCC pins that are currently used by porta and portb where you could move jtag and put TCK on a clock capable pin.
    Hello,

    I did as you adviced me and change location of JTAG TCK pin to W5 of Artix7 (GPIO pin 36 of my FPGA board)

    :
    Code:
    set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { TCK }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
    After that I removed directive:
    Code:
    #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK_IBUF]
    Now during implementation I haven't any warnings realted to JTAP programer TCK (clock) pin.
    Thanks for your help

    Regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK_IBUF]
    If this is exactly the directive you removed, it was doing nothing as it is commented out (in tcl, comment are #)



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Quote Originally Posted by TrickyDicky View Post
    If this is exactly the directive you removed, it was doing nothing as it is commented out (in tcl, comment are #)
    there wasn't as first letter the # - and it wasn't a comment (I commented this later) ;)

    Regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Did you have a specific question?



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Hello,

    I was very busy last two weeks (business trip) and haven't time to check programming AVR soft-core with using JTAG programmer. I am looking for board description for "Arduino IDE" which has ATMega103 MCU, but so far it wasn't successful. Also "Atmel Studio" (version 7 and 6) hasn't this MCU in therir list of programming targets. I think that answer is on web page:

    http://forum.arduino.cc

    but unfortunatelly this page is off-line.

    Has somebody a knowledge how to program ATMega1003 MCU using JTAG programmer? Where to find package with board description for ATMega103 for Arduino IDE?

    Kind regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Hello,

    little update: ATMega103 haven't JTAG interface, it is likely that this AVR soft-core should be programmed by JTAG programmer as ATMega128 (ATMega103 and ATMega128 are very similiar in inner structure).

    Regards



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    An advice....
    You can assemble your experience and later create a "Blog Entry" in this forum.
    Better than updating a thread....

    Creating separate threads puts more focus to the actual problem/question.
    FPGA enthusiast!



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Creating separate threads puts more focus to the actual problem/question.
    No good suggestion, IMHO. I'd stay with forum rules in this regard:
    Duplicates or cross posting are not allowed, avoid creating multiple threads with similar questions, ask all related questions in one thread.
    The idea is to keep the question context and support forum clearness.

    I agree that a blog might be appropriate for the topic. But presently there are questions to be answered.



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Xilinx FPGA have integreted CPUs, like microblaze, freertos, linux,...
    If you want to use Xilinx FPGA for developing, you can use microblaze CPU.
    If you want to use AVR for developing, you can buy AVR chip.
    Why do you need compile AVR-CPU in Xilinx FPGA?



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    Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    Quote Originally Posted by luoyanghero View Post
    Xilinx FPGA have integreted CPUs, like microblaze, freertos, linux,...
    If you want to use Xilinx FPGA for developing, you can use microblaze CPU.
    If you want to use AVR for developing, you can buy AVR chip.
    Why do you need compile AVR-CPU in Xilinx FPGA?
    Hello,

    first of all I am sorry for answering with big delay, but I didn't notice your post. I used Microblaze few times in my designs with Xilinx FPGAs, I aslo have a board with Xilinx Zynq SoC. I have many AVR boards (also few Arduino boards) and I am able to program them with C/C++ language.

    Why do you need compile AVR-CPU in Xilinx FPGA?
    Because I have fun doing it The second reason is to gain knowledge how to design soft-processor which is compatible with AVR family. I would like to extend this existing AVR-core - add VGA framebuffer. I hope I will be able to use Arduino libraries with this soft-CPU.

    Best Regards

    BTW: I am still waiting for JTAG AVR programmer - because of this "coronavirus" disease the time I am waiting for parcel increased (I bought it on Aliexpress in China).
    Last edited by FlyingDutch; 16th February 2020 at 09:28.



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