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  1. #1
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    FATAL ERROR while loading design in VHDL

    Code VHDL - [expand]
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    library ieee;                                -- line 1
    use ieee.std_logic_1164.all;                 -- line 2
                                                 -- line 3
    entity find_errors is 
    port(                                        -- line 4
        a: in std_logic_vector(0 to 3);             -- line 5
        b: out std_logic_vector(3 to 0);         -- line 6
        c: in std_logic_vector(5 downto 0));           -- line 7
    end find_errors;                                -- line 8
                                                 -- line 9
    architecture not_good of find_errors is         -- line 10
      begin                                      -- line 11
      my_label: process                          -- line 12
        begin                                    -- line 13
        if (c = ("00" & x"F")) then            -- line 14
          b <= a;                              -- line 15
        else                                     -- line 16
         b <= "0101";                            -- line 17
        end if;                                  -- line 18
      end process;                               -- line 19
    end not_good;
    Last edited by bassa; 4th January 2020 at 16:08. Reason: add code syntax

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  2. #2
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    Re: FATAL ERROR while loading design in VHDL

    Signals a and b are not assignment compatible, different index direction. This needs to be corrected at least.

    I'm sure your compiler or simulator gives a detailed error message with source line reference, you forgot to post it.



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  3. #3
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    Re: FATAL ERROR while loading design in VHDL

    The error is because your process has no sensitivity list or wait statement. This means it loops forever and probably hits the simulator iteration limit. you need to put C and A in the process sentivity list:

    Code VHDL - [expand]
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    my_label : process(a,c)

    Quote Originally Posted by FvM
    Signals a and b are not assignment compatible, different index direction.
    This is not a syntax or runtime error. Assigning arrays with opposite directions of the same size is perfectly fine, though it can often be a user error. Assignments will always assign 'left to 'right, so in the OPs case, b(3) = a(0) etc.


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  4. #4
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    Re: FATAL ERROR while loading design in VHDL

    This is an assignment from a coursera course. They use the same example for the quiz and for the "fix-it" assignment.

    There are at least two remaining errors. Probably three or four, but the latter two are based on knowledge of the assignment.



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