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Circuit to delay and shorten pulses of a pulse train?

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treez

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Hi
We have pulses which we need to delay by some approx. 280ns, and indeed we need to make the pulses shorter, again by some approx. 280ns
The attached (ltspice sim and pdf) show two circuits which could possibly achieve this.
Do you agree that the top circuit, which uses a logic buffer IC, is not workable in reality due to the high output impedance of the buffer? The SN74LVC1G17 datasheet suggests that at 5vin, its output resistance is 5V/0.032A = 156 Ohms…this is too high in this circuit.
Due to this, a FET gate driver IC must instead be used, as in the bottom circuit…(due to its definite low output resistance) ….would you agree?

SN74LVC1G17 logic buffer IC
https://www.ti.com/lit/ds/symlink/sn74lvc1g17.pdf
 

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A correct datasheet reading reveals an output resistance < 20 ohms. In so far the impedance level implemented in your circuit is well feasible. However if you worry about gate output current, why no increase the impedance by factor 5 - 10?
 
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Thanks, for SN74LVC1G17 i see IOH = 32mA for Vcc = 4.5V....thats 140 Ohms? (for output impedance)
 

Hi,

Thanks, for SN74LVC1G17 i see IOH = 32mA for Vcc = 4.5V....thats 140 Ohms? (for output impedance)
No, this is comlete impedance, which is output_impedance + load_impedance.

Since output voltage = 3.8V @ Vcc= 4,5V and I_OH = -32mA...
* Load impedance = 3.8V / 32mA = 119 Ohms
* Output impedance = (4.5V - 3.8V) / 32 mA = 22 Ohms

Klaus
 
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I have a schematic similar to yours. My simulation shows the incoming signal sources 1mA. It sinks 6mA.

input goes hi 1 MHz output delayed 280 nSec.png
 
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