2channelkrt
Newbie level 1
Hello, I'm fairly new in this Synopsys world.
I had a chance to use DC and ICC a lot these days, and am trying to validate my design.
Wrote in verilog, through DC, to ICC.
So I have a question and had nowhere to ask other than this place here..
I know there's lot of requirements to be met in order to declare certain design to be 'valid' (when physically fabricated, to be working).
When ICC finishes compiling my design, there's lot of references to check the timing.
First, Reading the result from typing 'report_timing' to the ICC console, which shows fair amount of scenarios and tells whether 'Slack' is negative(not valid) or positive(valid).
Second, Reading one of output files named something like 'chip_finish.timing_max' which is created by provided script from anonymous predecessor, which I haven't checked which script exactly makes that file. It also provides 3~4 cases of path slack, each with its own data_required_time and data_arrival_time with different values.
So, of which I should be looking in to? I'm pretty sure every slack should be positive, but unsure of which is more dominative.
If I set my clk to be 1 (1GHz) in above scenario, can I still say 'DC says my design runs in 1GHz!' even if one of timing results' 'data_required_time and data_arrival_time' is '1.1 and 1.09'? I am aware that DC result is far from correct compared to ICC result.
To bring ICC, my confusion deepenes.. For instance, I had my design's clk to be 0.5 (which should be 2GHz) in DC. In DC, slack was met and data required time was something like 0.47, so I move onto ICC.
When ICC was done compiling using the files from DC, result differs from time to time. I know if you use more than one thread during compile time, result becomes undeterministic. One time data_required_time:data_arrival_time becomes 0.43:0.36(slack met) and other times 0.56:0.54(slack met).
In either scenario, can I say my design runs in 2GHz despite of latter scenario, data_arrival_time is longer than 0.5? If 0.43:0.36 was the result, can I say my design runs in 2.1GHz? or is it just 2GHz from DC input option?
I also found a case where DC puts negative slack in timing (like 0.05) and when I put that result into ICC, slack becomes positive. I guess this is possible because DC is more vaguely assuming the timings through synthesis?
I haven't found any input options in ICC to tell the frequency of clk, so I'm not sure.
Thanks in advance, this site has been really helpful.
I had a chance to use DC and ICC a lot these days, and am trying to validate my design.
Wrote in verilog, through DC, to ICC.
So I have a question and had nowhere to ask other than this place here..
I know there's lot of requirements to be met in order to declare certain design to be 'valid' (when physically fabricated, to be working).
When ICC finishes compiling my design, there's lot of references to check the timing.
First, Reading the result from typing 'report_timing' to the ICC console, which shows fair amount of scenarios and tells whether 'Slack' is negative(not valid) or positive(valid).
Second, Reading one of output files named something like 'chip_finish.timing_max' which is created by provided script from anonymous predecessor, which I haven't checked which script exactly makes that file. It also provides 3~4 cases of path slack, each with its own data_required_time and data_arrival_time with different values.
So, of which I should be looking in to? I'm pretty sure every slack should be positive, but unsure of which is more dominative.
If I set my clk to be 1 (1GHz) in above scenario, can I still say 'DC says my design runs in 1GHz!' even if one of timing results' 'data_required_time and data_arrival_time' is '1.1 and 1.09'? I am aware that DC result is far from correct compared to ICC result.
To bring ICC, my confusion deepenes.. For instance, I had my design's clk to be 0.5 (which should be 2GHz) in DC. In DC, slack was met and data required time was something like 0.47, so I move onto ICC.
When ICC was done compiling using the files from DC, result differs from time to time. I know if you use more than one thread during compile time, result becomes undeterministic. One time data_required_time:data_arrival_time becomes 0.43:0.36(slack met) and other times 0.56:0.54(slack met).
In either scenario, can I say my design runs in 2GHz despite of latter scenario, data_arrival_time is longer than 0.5? If 0.43:0.36 was the result, can I say my design runs in 2.1GHz? or is it just 2GHz from DC input option?
I also found a case where DC puts negative slack in timing (like 0.05) and when I put that result into ICC, slack becomes positive. I guess this is possible because DC is more vaguely assuming the timings through synthesis?
I haven't found any input options in ICC to tell the frequency of clk, so I'm not sure.
Thanks in advance, this site has been really helpful.
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