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Output offset problems in folded cascode differential amplifier.

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Sambhav_1

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Hi,
I am designing a differential folded cascode with both P and N-mos input transistor stages due to my different input common modes.
During my transient analysis while running across the corners i am getting some offset of 70mv at worst between the two outputs.
How can i minimize this offset.
Note: I am giving a 0.3mV offset at the input and these results are in pre layout simulations.
Thanks
 

If the gain of your amplifier is about 47dB than the 70mv at output is just the amplified 0.3mV input offset. I assume this is not a Monte-Carlo simulation, so whatever offset you are getting, besides the amplified input offset is just some systematic asymmetry.
 

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