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    Verilog modulus % operator

    I'm failing LEC on registers that are equal to A%B construct. Where B is not a power of 2. I've read in several forums and online articles that some synthesizers do not support non-power of 2 modulus. But I have yet to find that stated in a Cadence or Synopsys document. Do these synthesizers support non-power of 2 modulus? A doc link it appreciated.

    Thanks

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    Re: Verilog modulus % operator

    Quote Originally Posted by TonyLS View Post
    I'm failing LEC on registers that are equal to A%B construct. Where B is not a power of 2. I've read in several forums and online articles that some synthesizers do not support non-power of 2 modulus. But I have yet to find that stated in a Cadence or Synopsys document. Do these synthesizers support non-power of 2 modulus? A doc link it appreciated.

    Thanks
    I think you won't find that precise of a statement in any of the vendors' documents since they have synthetic/designware libraries that support a lot of arithmetic functions, including modulus. See Dw_div here: https://www.synopsys.com/dw/buildingblock.php
    Really, I am not Sam.


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    Re: Verilog modulus % operator

    Quote Originally Posted by ThisIsNotSam View Post
    I think you won't find that precise of a statement in any of the vendors' documents since they have synthetic/designware libraries that support a lot of arithmetic functions, including modulus. See Dw_div here: https://www.synopsys.com/dw/buildingblock.php
    Thanks for the link. I don't see any restrictions on what the modulus needs to be within the Synopsys Dw_div datasheet. I'll look for the Cadence datasheet. The design is being synthesized with Cadence tools.The same verilog module that has the modulus construct is instantiated many times. The two instantiations that are failing have a non-power of 2 modulus, the passing ones have a power of 2.

    Thanks



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    Re: Verilog modulus % operator

    You didn't yet mention which error is shown by Synopsys.



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    Re: Verilog modulus % operator

    Quote Originally Posted by FvM View Post
    You didn't yet mention which error is shown by Synopsys.
    I mentioned that LEC is failing. Logic Equivalence Checking between the verilog RTL and the synthesized gate netlist. The LEC tool and synthesizer are Cadence tools.

    Thanks



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  6. #6
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    Re: Verilog modulus % operator

    Sorry, my ignorance. But the error doesn't seem to be specific for missing synthesis support.



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