Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog modulus % operator

Status
Not open for further replies.

TonyLS

Member level 3
Joined
Jan 21, 2009
Messages
58
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
Boston, MA
Activity points
1,760
I'm failing LEC on registers that are equal to A%B construct. Where B is not a power of 2. I've read in several forums and online articles that some synthesizers do not support non-power of 2 modulus. But I have yet to find that stated in a Cadence or Synopsys document. Do these synthesizers support non-power of 2 modulus? A doc link it appreciated.

Thanks
 

I'm failing LEC on registers that are equal to A%B construct. Where B is not a power of 2. I've read in several forums and online articles that some synthesizers do not support non-power of 2 modulus. But I have yet to find that stated in a Cadence or Synopsys document. Do these synthesizers support non-power of 2 modulus? A doc link it appreciated.

Thanks

I think you won't find that precise of a statement in any of the vendors' documents since they have synthetic/designware libraries that support a lot of arithmetic functions, including modulus. See Dw_div here: https://www.synopsys.com/dw/buildingblock.php
 
  • Like
Reactions: FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
I think you won't find that precise of a statement in any of the vendors' documents since they have synthetic/designware libraries that support a lot of arithmetic functions, including modulus. See Dw_div here: https://www.synopsys.com/dw/buildingblock.php

Thanks for the link. I don't see any restrictions on what the modulus needs to be within the Synopsys Dw_div datasheet. I'll look for the Cadence datasheet. The design is being synthesized with Cadence tools.The same verilog module that has the modulus construct is instantiated many times. The two instantiations that are failing have a non-power of 2 modulus, the passing ones have a power of 2.

Thanks
 

You didn't yet mention which error is shown by Synopsys.
 

You didn't yet mention which error is shown by Synopsys.

I mentioned that LEC is failing. Logic Equivalence Checking between the verilog RTL and the synthesized gate netlist. The LEC tool and synthesizer are Cadence tools.

Thanks
 

Sorry, my ignorance. But the error doesn't seem to be specific for missing synthesis support.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top