akbarza
Full Member level 2
hi
i saw in a file( i did not find the file again) that for layout of nmos transistor , two polysilicon layers was used for connection of gate to other segments.
why two or more polysilicon is used for gate in cmos transistor layout?also why multi layers of metal is used for connection source or drain to other segment?
excuse me if this question is crazy, but i had the question.
thanks
i saw in a file( i did not find the file again) that for layout of nmos transistor , two polysilicon layers was used for connection of gate to other segments.
why two or more polysilicon is used for gate in cmos transistor layout?also why multi layers of metal is used for connection source or drain to other segment?
excuse me if this question is crazy, but i had the question.
thanks