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  1. #1
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    Two polysilicon layers for gate connection

    hi
    i saw in a file( i did not find the file again) that for layout of nmos transistor , two polysilicon layers was used for connection of gate to other segments.
    why two or more polysilicon is used for gate in cmos transistor layout?also why multi layers of metal is used for connection source or drain to other segment?
    excuse me if this question is crazy, but i had the question.
    thanks

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  2. #2
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    Re: Two polysilicon layers for gate connection

    Dual poly has been a sometime feature of mixed signal CMOS
    processes, used to make poly-poly (POP) capacitors that
    don't block metal routing. In these days of >10 metal levels
    the MIM capacitor has pretty much displaced the POP cap
    with its inferior series resistance and lower C/area (thicker
    oxide for reliability, due to poly surface roughness etc.).

    In such flows only the lower poly is used for the gate electrode.
    The upper poly is special-purpose and often only contactable
    by Met1.

    There are sometimes multiple poly "layers" which are for doped
    poly, in cases where this is distinct from the S/D doping shots
    (for example maybe the flow wants depletion mode FETs which
    want poly doped differently than logic FETs, then you have a
    N poly and a P poly mask, but in the end it's just one layer put
    together with Booleans (plus two soft-mask implant levels);
    check the mask generation logic if it is disclosed in the LGRP).

    Use of multiple Met layers may be an antenna-rules best practice,
    could be for some routing convenience that you are not shown
    at the level you're at, etc.


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  3. #3
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    Re: Two polysilicon layers for gate connection

    If there are many metal layers in a process (let's say, 10 or 15), lower metal layers are thin and highly resistive, and upper metal layers are thick and low resistive.
    That's why top metal layers are used for lateral routing of source and drain nets.
    To get down to active devices, one has to go through all other metal layers, vertically.
    That's why all metal layers get used: top layers - mostly for lateral routing, lower metal layers - mostly for vertical routing.

    The same is true not only for source/drain nets. but for other nets as well - gate, power, clocks, etc.


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