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    Simulating the slew rate with capacitive feedback fully differential amplifier

    Hello,

    I am simulating the slew rate of fully differential OTA. I have a problem with making buffer using resistive network, first I can't choose small value of R because this will kill the gain of the OTA, secondly if I use a big resistors it creates in conjunction with the input MOSFET a pole at low frequency that disturb the stability of my amplifier.

    By looking in to this problem I have serched and found many authors are testing the lsew rate using pure capacitive network as shown in the figure below,

    Click image for larger version. 

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    My question is what is the total effective or equivalent capacitive load seen at the differential output ?

    My second question, can we simulate the slew rate from open loop ? I belive that we can but we will not get an information about phase margin and GBW

    Thank you very much

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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Slew rate would want both output loading and input overdrive
    specified as conditions. I'd suggest looking at some commercial
    FDOA datasheets for cues. You may not find many low voltage
    OTAs out there however, these are more of an inside-analog-ASIC
    item than a general purpose solution (as you note, very load
    sensitive).

    If you know the load, simulate the load. If nobody's telling you
    what the load is, then industry standard behavior is to set the
    conditions such that they make you look good, without being
    unacceptably greedy / limiting to the end user. Like, if ADI's
    op amp says 1000V/us at CL=10pF, you're doing yourself no
    favors by specing at CL=20pF and reporting 600V/us - maybe
    one user in 10 notices the conditions, the rest just think you
    offer an inferior-speed product.


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear freebird,

    Thank you for your reply

    that was nice explanation,

    my load is 10 PF, so according to the circuit in the graph is c2= 10 PF. but I don"t know how much should I use for C1, or the effective load on vo with including the feedback capacitors



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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    At the output, looking into each output you will see C2 in parallel with the effective capacitance seen looking backwards into the feedback cap C1. If you define a feedback factor b=C1/(C1+C1+Cin), where Cin is the input cap of the OTA to ground, then looking back into C1 you will see Ceff=(1-b)C1. Then your load cap for each output is C2+Ceff.

    When it comes to slew rate, you should give a large voltage step at the input of the circuit. Since step edge is very sharp, the OTA will not be able to respond to that and then at the input of the OTA you'll see instantaneously a corresponding step defined just by the capacitive divider, as if the OTA was not even there. If the OTA input step is bigger than about sgrt(2)Vov of the input diff pair, then the OTA will slew. So, just give a large enough step to make it slew and look at the results.


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Quote Originally Posted by sutapanaki View Post
    At the output, looking into each output you will see C2 in parallel with the effective capacitance seen looking backwards into the feedback cap C1. If you define a feedback factor b=C1/(C1+C1+Cin), where Cin is the input cap of the OTA to ground, then looking back into C1 you will see Ceff=(1-b)C1. Then your load cap for each output is C2+Ceff.

    When it comes to slew rate, you should give a large voltage step at the input of the circuit. Since step edge is very sharp, the OTA will not be able to respond to that and then at the input of the OTA you'll see instantaneously a corresponding step defined just by the capacitive divider, as if the OTA was not even there. If the OTA input step is bigger than about sgrt(2)Vov of the input diff pair, then the OTA will slew. So, just give a large enough step to make it slew and look at the results.
    Dear Suta,
    Thank you very much for your explanation,

    I have a question about the Ceff, first when you tried to find b (the feedback factor) you have treated the capacitor as a resistor in series and you used the voltage devider rule ?

    Second, I have used a C1 = 0.5 pf and C2 = 10 pF. When I apply a square wave I see my outputs are two square waves out of phase but they are not symetrical around VCM wich is the output commom mode voltage, mean the two signals looks one above each other but they dont intersect. I changed the signal to sin input signal and the outputs are fine symetrical around VCM

    I dont know what this mean and why



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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    It is actually a capacitive divider. Or rather an impedance divider of which the resistive divider or a capacitive divides are just particular cases.

    Maybe you can post a picture of your test bench and results here.


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear Suta,

    Here is the circuit with the result, as you see that is strangely the outputs are not intersecting in the middle. This is not the case when I apply a sin signal instead of the pulse signal,

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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    1. I see how you set your output common mode, but how do you set the common mode (i.e. DC bias) at the inputs of the amplifier?
    2. Have you looked inside the amplifier at the time when the two outputs are the same at 1.65V (half of the period) and see what the currents are and the voltages too. Maybe this will give you a clue why you don't see a differential voltage for that time. How do the OTA inputs look like for that half of the period.
    3. Have you try decreasing the input amplitude, say not 500mV but 50mV for example? Do you still get the same behavior?


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear Suta,

    Tnhank you for your reply,

    1. The DC biasing of the common mode input signals is set by the balun, so I am applying a differential input pulse signals with a common mode voltage equal to 1.65 V,

    Regarding your points 2 and 3 I need to see it in the lab

    but as I told you there is no problem when I apply a sine signals with the same setup, only this problem apears with the pulse signals



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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    OK, but between the balun and the OTA inputs you have a capacitor which blocks DC bias. So, looks to me there is nothing that really biases the inputs of the OTA which can be a problem. When you try 2) and 3) above, can you also try one other thing. Put a resistor, say 100MOhm in parallel to the input C1 so you have a DC path between the balun and the inputs. THis is just for simulation, I'm not suggesting it for the final design. See what happens with that resistor. Of course there will be some initial transient and also droop in the pulse amplitude but at least you can see if it makes things differential.


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear Suta,

    I think now you put your hand on the right investigation,

    I connected a big resistor in parallel to the C1 (at the input side only), the result was vrey degraded, I changed the value to 1 kOhm

    The result is shown below for the tow differential outputs, now they are correctly slewing, however, they are approaching the rails which means that gain is not becoming unity

    Click image for larger version. 

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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    What do you mean by result being degraded? I assume you see the initial transient. You should probably simulate for much longer than 17.5us because 100MOhm with 0.5pF results in timeconstant of 50us. When you put 1kOhm resistor, then the capacitor is practically shunted and you have an integrator - 1k resistor and the feedback capacitor. The UGBW of the integrator is something like 320MHz, which means that the gain at 1MHz is 50dB. That's the reason why I suggested 100MOhm resistor. Actually, you can set initial conditions of 1.65V for the two OTA inputs and this will most probably speed up the transient.


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear Suta,

    I will try your suggestion by tomorrow

    thanks alot for your nice help



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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Quote Originally Posted by sutapanaki View Post
    What do you mean by result being degraded? I assume you see the initial transient. You should probably simulate for much longer than 17.5us because 100MOhm with 0.5pF results in timeconstant of 50us. When you put 1kOhm resistor, then the capacitor is practically shunted and you have an integrator - 1k resistor and the feedback capacitor. The UGBW of the integrator is something like 320MHz, which means that the gain at 1MHz is 50dB. That's the reason why I suggested 100MOhm resistor. Actually, you can set initial conditions of 1.65V for the two OTA inputs and this will most probably speed up the transient.
    I put the 100 MOhm as you suggested , I made the simulation time for 1ms, see the result please

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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    OK, this is not what I expected. One output is stuck at supply. I think it is time now to do 2) and 3) from my post #8

    - - - Updated - - -

    By the way, it will be good if you can plot the inputs of the OTA and put corresponding inputs, outputs in one plot, so you can see if they are differential.


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Here is what I think happens in the setup from your post #7. Your circuit is with a capacitive only feedback and thus only responds to signal changes, not to low frequency or DC. Your simulation starts initially at the common mode at the output which is 1.65V. I even think that probably the simulator somehow calculates the OTA input (i.e. the summing junction) common-mode voltage also at 1.65, but it can be anything because it is a floating node. Anyway, one of your single ended inputs jumps up by 500mV and the other down by 500mV. The amplifier gain is 1, so the single-ended outputs, one of them goes down by 500mV and the other goes up by 500mV, respectively. On the next transition your inputs go in the opposite direction by 500mV and so do the outputs. So the output that has gone previously up by 500mV, now has to go down by 500mV and doing so ends up at the common-mode voltage, where it started initially. In the same way, the other output that has gone down before now goes up by 500mV and also ends up at the common mode. So, you have the behavior that you showed.
    Can you try this time to connect a big resistor, 100M in parallel with the feedback capacitors and wait long enough for the transient to die out. What do you get?


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear Suta,

    That is exactly what I have seen in this paper,

    https://ieeexplore.ieee.org/document/8805570

    with this setup the circuit is working as expected with gain is equal to unity

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    next I will try to change the gain by changing the resistor ratios and update you with the result

    - - - Updated - - -

    I just simulated it right now again with gain equal to one by making R1=50 MOhm and again circuits needs adjusment, if I decrease the input R to the half I must double the input C1 to give the accurate result as shown below

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    - - - Updated - - -

    meanwhile, I have seen one author trying to solve the DC biasing problem a the input by providing the common mode voltage thraugh a voltage devider with big resistors as shown below, but in my case it was not prooven, means I get the origional problem

    Click image for larger version. 

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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Actually, I had in mind leaving only the feedback resistor and removing the one in parallel with the input capacitor. In this case the output common-mode will define also the input common mode. The cap ratio will define the gain, but you'll have a high pass gain characteristic with a corner frequency defined by the R and C1

    By the way, what is the intended application of this amplifier?


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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Dear Suta,
    Thank you for your help
    Attached below is the setup according your last suggestion, again the output is missing the symetry arounf VCM. by the way I have noticed with this configuration that AV(closed)=C1(input)/C1(feedback) which is reverse to the theoritical low ??

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    The intended application is to build fully differential sample and hold circuit



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    Re: Simulating the slew rate with capacitive feedback fully differential amplifier

    Hi,

    AV(closed)=C1(input)/C1(feedback) which is reverse to the theoritical low ??
    Why reverse?

    The bigger the C the lower the impedance.

    Usually: A = R_fb/ R_in....in your case it is: A= X_fb / X_in.....nothing reversed.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.


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