# Counter cİrcuİt (3 forward 2 back)

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2. ## Re: Counter cİrcuİt (3 forward 2 back)

A counter is made from D flip-flops (JK type can be used). (Four creates a nibble, enough to make 16 different digits on a 7-segment display.)

To count down, gather outputs from Q pins. Feed to a 7447 IC. The outputs drive a 7-segment display.
To count up, gather outputs from not-Q.

Your cycle has 5 steps (increment by one 3 times, decrement by one 2 times). Run a separate counter which counts from 0 to 4 then recycles. Use logic gates to determine which outputs you need gather, whether you're currently incrementing by 1, or else decrementing by 1.

There's a lapse in my approach because the number at the Q pins is different from the number at the not-Q pins. So something further needs to be figured out.

Did you experiment with D FF's arranged to create binary patterns? It's different from a shift register, of course.

3. ## Re: Counter cİrcuİt (3 forward 2 back)

Hi,

Simple answer: use a microcontroller and write the correct code.

If you want a more detailed answer, then give all your requirements first.
10 words are simply not enough.

Don't expect a more detailed anser than your question.

Klaus

4. ## Re: Counter cİrcuİt (3 forward 2 back)

No matter how a possible counter circuit is implemented (discrete logic gates, programmable logic, microcontroller, transistors), it's primarily logic design problem.

3 forward, 2 back means you have a state machine with at least five sequential states, >= 3 state bits (or FFs), depending on the state encoding. But how many counter bits?

5. ## Re: Counter cİrcuİt (3 forward 2 back)

another possibility could be to consider the counter as a state machine with two states: up and down. It could be something like that
process(clk)
begin
if clk = '1' and clk'event then
if up = '1' then
cnt <= cnt + 1;
if cnt = 1 then
up <= '0';
end if;
else
cnt <= cnt - 1;
if cnt = 1 then
up <= '1';
end if;
end if;
end if;
end process;

6. ## Re: Counter cİrcuİt (3 forward 2 back)

another possibility could be to consider the counter as a state machine with two states: up and down. It could be something like that
You didn't actually test your design idea. It doesn't work.

The design should generate this sequence

You see that there's no relation between forward-backward state and counter value, the counter is advancing one net count after cycling through the five states. Respectively it's not possible to derive the next state based on the counter value. There has to be a state machine independent of the counter.

7. ## Re: Counter cİrcuİt (3 forward 2 back)

Hi,

It is quite simple to implement this. You need to have a counter, a direction signal and a comparator. Of course you would need clock and reset signals. Now, when the direction is forward, you increment the counter. When the counter value is 2 (i.e. the third count, having gone through states 0, 1, and now, 2) and the direction is forward, then you make the direction back and you reset the counter.

When the direction is backward and the counter value is 1 (i.e. the second count, having gone through 0, and now, 1), then you make the direction forward and you reset the counter.

I haven't mentioned that the logic is sensitive to the clock signal and I how you picture that it is.

8. ## Re: Counter cİrcuİt (3 forward 2 back)

assuming the counter starts at 0,
you count 3 forward, 1, 2, 3
then 2 back, 2, 1

now what?
does it stop?

does it do it again?
count 3 forward, 2, 3, 4
then 2 back, 3, 2

and then what?

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9. ## Re: Counter cİrcuİt (3 forward 2 back)

Hi there.

You do difficult stuff, so I hope either pdf gives you some clues as to how to implement this. As said various times already, truth tables and their results and/or Karnaugh tables and thinking = flipflops + simple logic gates + clock(s) + shift circuitry from counting up at #3 to counting down twice. Easier said than done. That or the MCU recommended...

If it is a repetitive 3 up 2 down forever function, why not start from the notion of a 'clockwork toy'? Might make it all less daunting to tackle...

Maybe perusing datasheets and app notes for up/down counters will help, too, such as the: https://www.nexperia.com/products/an...74HC191PW.html

Counter circuits.pdfDigital_Electronics_09_pdf.pdf

10. ## Re: Counter cİrcuİt (3 forward 2 back)

Hi,

8 posts now without reaction of the OP.
It seems the OP is not interested in communication.

And we may discuss endlessly about the lack of information...

Klaus

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11. ## Re: Counter cİrcuİt (3 forward 2 back)

Hi Klaus,

Long time no see, hope you're very well.

Originally Posted by KlausST
Hi,

8 posts now without reaction of the OP.
It seems the OP is not interested in communication.

And we may discuss endlessly about the lack of information...

Klaus
As they say in Spanish, more or less: Those who remain silent are in agreement with what was said... I'm staying silent about your observation ;). Anyway, I'll add a silly block diagram with possible errors of reasoning, in case it helps them...

Best regards.

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Hi again,

I quite like circuits such as the one you wish to implement...

This is a hurried block diagram of the recurrent premise in this whole thread of helpful answers, there may be mistakes in my doodle as it is a general idea to consider and also think out glitches from unexpected sequences such as 2 up then 2 down then 1 up, unless your goal really is 3 up then 2 down then repeat forever. Useless and basic as it may be, hope it can be of use whether designed on a circuit or a code level. Good luck

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... Whoops, that thing that looks like a children's drawing (sadly, I did it!) was meant for electricc01, not Klaus who is an experienced engineer, obviously...

12. ## Re: Counter cİrcuİt (3 forward 2 back)

Hi,

... Whoops, that thing that looks like a children's drawing (sadly, I did it!) was meant for electricc01, not Klaus who is an experienced engineer, obviously..
I like schematics. For sure the "software drawn" are more nice, but often they don't contain more informations than hand drawn.

Thus - in many threads I've recommended to take a piece of paper and a pencil.
I think it's a good method to rectify one owns ideas. Especially for the not highly experienced.
I by myself use it frequently.

Klaus

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13. ## Re: Counter cİrcuİt (3 forward 2 back)

Originally Posted by Akanimo
Hi,

It is quite simple to implement this. You need to have a counter, a direction signal and a comparator. Of course you would need clock and reset signals. Now, when the direction is forward, you increment the counter. When the counter value is 2 (i.e. the third count, having gone through states 0, 1, and now, 2) and the direction is forward, then you make the direction back and you reset the counter.

When the direction is backward and the counter value is 1 (i.e. the second count, having gone through 0, and now, 1), then you make the direction forward and you reset the counter.

I haven't mentioned that the logic is sensitive to the clock signal and I how you picture that it is.
If you need to count up and down in an incremental fashion, then you would add an up-down counter to the circuit. Increment the up-down counter when direction signal is forward and backward-forward counter value is 2, or when direction is backward and backward-forward counter value is 0. Decrement when direction is backward and backward-forward counter value is 1, or when direction is forward and backward-forward counter value is less than 2.

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14. ## Re: Counter cİrcuİt (3 forward 2 back)

Originally Posted by FvM

The design should generate this sequence

For that sequence, the code could be:
```Code VHDL - [expand]1
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process(clk)
begin
if clk = '1' and clk'event then
cnt_int <= cnt + 1;
if up = '1' then
if cnt_int = 2 then
cnt_int <= (others => '0');
up <= '0';
end if;
else -- down
if cnt_int = 1 then
cnt_int <= (others => '0');
end if;
end if;
if up = '1' then
cnt <= cnt + 1;
else
cnt <= cnt - 1;
end if;
end if;
end process;```

@electricc01, could you provide more details on the sequence you would like to generate?

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15. ## Re: Counter cİrcuİt (3 forward 2 back)

Looks correct, except for missing assignment up <= '1' after line 12. There should be also a reset clause initializing all signals.

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Forgot typo correction in line 4
cnt_int <= cnt_int + 1;

16. ## Re: Counter cİrcuİt (3 forward 2 back)

Originally Posted by Medea
For that sequence, the code could be:
```Code VHDL - [expand]1
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process(clk)
begin
if clk = '1' and clk'event then
cnt_int <= cnt + 1;
if up = '1' then
if cnt_int = 2 then
cnt_int <= (others => '0');
up <= '0';
end if;
else -- down
if cnt_int = 1 then
cnt_int <= (others => '0');
end if;
end if;
if up = '1' then
cnt <= cnt + 1;
else
cnt <= cnt - 1;
end if;
end if;
end process;```

@electricc01, could you provide more details on the sequence you would like to generate?
It doesn't seem to me like this is going to work. I see a conflict on cnt_int, especially because of where you chose to place the expression in line 4.

Also realize that the logic is sequential, so the conditions that toggle the direction bit from up to down and vice versa takes one clock cycle. Your code as it is will increment in error one clock cycle and decrement in error one clock cycle in every five clock cycles. With this, your final result might turn out to be correct after every five clock cycles but your count sequence would not be correct.

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Run a simulation and also take a look at post #7 and post #13.

17. ## Re: Counter cİrcuİt (3 forward 2 back)

With the suggested corrections in post #15, the code does what I would expect according to the original specification.

reset state: cnt = 0, cnt_int = 0, up = '1'

The counter shall count up three times 0->1, 1->2, 2->3, then count down twice 3->2, 2->1. The up again 1->2 …

Notice that the sequence shown in post #6 and #14 shows the new cnt value after each clock cycle. This might have caused your doubts about wrong timing. At the end of the day, the generated cnt sequence matters, the internal state representation may be different.

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18. ## Re: Counter cİrcuİt (3 forward 2 back)

I now get the point that you are considering cnt_int = 0 as the reset state and you start the count from cnt_int = 1. I was considering cnt_int = 1 to be the start of the count.

Clear doubts that I have about the code is that I can see where the direction (up) is toggled from '1' to '0' on line 8, but there is no where that it is toggled from '0' to '1'.

Also, I see conflict with the increment of cnt_int with clock on line 4 and its conditional reset on line 7 and line 12.

I will run a simulation and come back with the result.

19. ## Re: Counter cİrcuİt (3 forward 2 back)

Originally Posted by Akanimo
... I was considering cnt_int = 1 to be the start of the count...
I'm sorry. I meant cnt_int = 0...

20. ## Re: Counter cİrcuİt (3 forward 2 back)

I can see where the direction (up) is toggled from '1' to '0' on line 8, but there is no where that it is toggled from '0' to '1'.
A necessary correction, see post #15.

Also, I see conflict with the increment of cnt_int with clock on line 4 and its conditional reset on line 7 and line 12.
What do you mean with conflict? According to VHDL rules the last assignment (reset) is executed.

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