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  1. #1
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    VHDL - creation of files with unique file names

    I have a test-bench module which is instantiated multiple times. In there is a file write operation. My requirement is to have an unique file created for each instantiated module.

    How can I do that?

    --------------------------------------------------------------------

    This is what I have done...

    The uniqueness of the file name is to be derived from two generics, SLOT_NUM and PORT_NUM.
    e.g. - file__SLOT_NUM__PORT_NUM

    Code:
    SLOT_NUM : integer  := 0;        
    PORT_NUM : std_logic_vector(1 downto 0) := "00" ;
    
    Inside the module I have the declaration,
    constant file_path              : string(1 to 40) := "C:\Work\elog\fpga_a7\sources\sim\frm_rx\";
    signal file_name                : string(1 to 13)          ;
    signal complete_file_path   : string(1 to 53)          ;
    file   outfile                       : text                         ; -- Declare write file variable, file pointer
    shared variable outline       : line                         ; -- line number declaration
    .
    .
    file_name <= "frm_rx_" & integer'image(SLOT_NUM) & integer'image(to_integer(unsigned(PORT_NUM))) & ".txt";   
        
    complete_file_path <= string'(file_path) & string'(file_name);

    Now I have like - file_open(outfile, string'(complete_file_path), write_mode); which does not work.

    The goal is to create and write to files such as
    C:\Work\elog\fpga_a7\sources\sim\frm_rx\file__0__0 .txt
    C:\Work\elog\fpga_a7\sources\sim\frm_rx\file__0__1 .txt
    C:\Work\elog\fpga_a7\sources\sim\frm_rx\file__1__0 .txt, and so on.

    I am doing those string'() explicit string casting to be on the safe side but they don't help.

    Vivado2019.2 complains this line: writeline(outfile, outline); -- Begin file write after 1 line space

    I suspect it has something to do with the file_open() procedure, because if I replace the complete_file_path by an explicit string like "....." at least the file is created.
    So what is the workaround?
    FPGA enthusiast!

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  2. #2
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    Re: VHDL - creation of files with unique file names

    You code doesnt show the problem line - it would be easier if you posted the full example.
    I will comment though that having the filename as a signal is rather odd. At time zero it will be all NUL, and wont have a value until some time in the future. Usually you just set the filename via constants, and probably without specifying the length. It means you dont need to know the length beforehand. Theres also no need to qualify the fact it is a string because FILE_OPEN only accepts a string. qualification is only needed when there are multiple methods that shared the same signature.

    Also, any reason you need line to be a shared variable? why cant it just be a variable inside a process (the same goes for the file). It means you wont have any '93/2002 incompatability.

    If it was me, I would do the following:

    Code VHDL - [expand]
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    SLOT_NUM : integer  := 0;        
    PORT_NUM : std_logic_vector(1 downto 0) := "00" ;
     
    constant FILE_BASE_PATH : string :=  "C:\Work\elog\fpga_a7\sources\sim\frm_rx";  -- length implied from literal
    constant FILE_PATH : string := FILE_BASE_PATH & "__" & integer'image(SLOT_NUM) & "__" & integer'image(to_integer(unsigned(PORT_NUM))) & ".txt";
     
    ....
     
    FILE_OPEN(outfile, FILE_PATH, WRITE_MODE);


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  3. #3
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    Re: VHDL - creation of files with unique file names

    Thanks for your inputs.
    will comment though that having the filename as a signal is rather odd.
    That was the problem. SLOT_NUM and PORT_NUM values are available at compile time and so the the string can be of constant type.

    Also, any reason you need line to be a shared variable?
    It was some copy + paste from some legacy code. I have removed it and just used used as a variable within a process.
    FPGA enthusiast!



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