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    Phase Detect Circuitry

    How is clk_dcc generated from the following phase detect circuitry ?


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    Re: Phase Detect Circuitry

    D flip-flop is frequently used to create a divide-by-2. Thus its output is 50 percent duty cycle (labelled clk_dcc).

    There are invert-gates in a feedback loop. It makes operation a bit more complicated. Is your question about their effect on the D FF?


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    Re: Phase Detect Circuitry

    There are invert-gates in a feedback loop. It makes operation a bit more complicated. Is your question about their effect on the D FF?
    @BradtheRad

    Could you explain more about the CMOS invert gate in the feedback loop ?



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    Re: Phase Detect Circuitry

    The rightmost invert-gate pulls the D pin hi or low, to drive flip-flop operation in a correct way that divides by 2.

    Usually a divide-by-2 schematic omits the invert-gate and connects D pin to Not-Q pin.
    However we might surmise that the invert-gates together create a slight delay function, seeing there are buffers in your schematic labelled with a delay function.

    Fast speeds (as 400MHz) can create delays simply due to propagation time in switching devices. Whereas, at slow speeds we usually see capacitors or inductors arranged clearly and understandably to form a delay network.



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