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  1. #1
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    Send one parameter from systemverilog to another in Vivado 2017.3

    greetings ... tell you that I am very new to systemverilog and I have some files to perform a simulation test for a project. This test has a main file stimulus.sv which creates an instance of another called local_g1_test_bench.sv, in this second file a vector is created for the differential clock that will be used in different modules, as follows.

    Code:
    reg sim_pim1_uclock0 = 1;//IEA Added
    reg sim_pim1_uclock1 = 1;//IEA Added  
    reg sim_pim1_uclock2 = 1;//IEA Added
    reg sim_pim1_uclock3 = 1;//IEA Added
      
    always//IEA Added
       #2500    sim_pim1_uclock0 = ~sim_pim1_uclock0; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #2500    sim_pim1_uclock1 = ~sim_pim1_uclock1; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #2500    sim_pim1_uclock2 = ~sim_pim1_uclock2; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #2500    sim_pim1_uclock3 = ~sim_pim1_uclock3; //  6.80 nS period 147.06 MHz NEW//IEA Added 
       
    //assign i_pim1_uclk_p =  {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
    //assign i_pim1_uclk_n = ~i_pim1_uclk_p;   
                   
    wire [3:0] pgm_user_clk_p = {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
    wire [3:0] pgm_user_clk_n = ~pgm_user_clk_p;
    I want to create the differential clock vector in the stimulus.sv file and send it to local_g1_test_bench.sv as a parameter. Could someone help me with some information to do this, please.
    I leave attached the files stimulus.sv and local_g1_test_bench.sv

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  2. #2
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    Re: Send one parameter from systemverilog to another in Vivado 2017.3

    I want to create the differential clock vector in the stimulus.sv file and send it to local_g1_test_bench.sv as a parameter.
    You can copy+paste the above stuff from local_g1_test_bench.sv to stimulus.sv
    Then use port mapping to transfer this diff clk from stimulus.sv to local_g1_test_bench.sv or other instances.
    FPGA enthusiast!



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  3. #3
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    Re: Send one parameter from systemverilog to another in Vivado 2017.3

    Thanks dpaul for responding, when making this change I am sending the differential clock as shown in the following code.

    Code:
    `timescale 100ps/100ps
    
    module stimulus();
    
    //===========================================================================================
    // Instantiate the test bench and sim_services().
    //===========================================================================================
    
    import sim_services_package::*;
    
    reg sim_pim1_uclock0 = 1;//IEA Added
    reg sim_pim1_uclock1 = 1;//IEA Added  
    reg sim_pim1_uclock2 = 1;//IEA Added
    reg sim_pim1_uclock3 = 1;//IEA Added
      
    always//IEA Added
       #2500    sim_pim1_uclock0 = ~sim_pim1_uclock0; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #2500    sim_pim1_uclock1 = ~sim_pim1_uclock1; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #2500    sim_pim1_uclock2 = ~sim_pim1_uclock2; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #2500    sim_pim1_uclock3 = ~sim_pim1_uclock3; //  6.80 nS period 147.06 MHz NEW//IEA Added 
       
    //assign i_pim1_uclk_p =  {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
    //assign i_pim1_uclk_n = ~i_pim1_uclk_p;   
                   
    wire [3:0] pgm_user_clk_p = {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
    wire [3:0] pgm_user_clk_n = ~pgm_user_clk_p;
    
    local_g1_test_bench u_local_g1_test_bench (
    
      .o_pim_uclk_p         ( pgm_user_clk_p        ),  // output   [3:0] //
      .o_pim_uclk_n         ( pgm_user_clk_n        )  // output   [3:0] //
    );
    
    
    initial
    begin
    
       u_sim_services = new();
    
       u_sim_services.set_test_name( "wtest_hotlink_pim1_rx_only_simple" );
    
       u_sim_services.set_test_description( "Tb generates hotlink rx messages. Verify Aurora sdma TLPs.");
    
       force u_local_g1_test_bench.failsafe_timeout_in_microseconds = 'd800;
    
       // Tell the EBC bus model to get going.
       u_local_g1_test_bench.EBC_GO = 1;
    
    
       // Tell the Aurora RX transactor to get going.
    
       wait( u_local_g1_test_bench.u_simulation_aurora_xactor_g1.u_xactor_core.o_aur_channel_up );
    
       u_local_g1_test_bench.AURORA_RX_GO = 1;
    
    
       // Enable the UUT to transmit BIT/Status messages
       u_local_g1_test_bench.hotlink_sim_enable = 1;
    
       
       #50000; // Delay 5uS = 5,000,000 ps/100ps 
    
       // Drive Timestamp_sync to TDF and transactors. For this simulation, align carefully so that
       // timestamp values evenly divisible by 4 align with rising edges of REFCLK.
    
       wait( u_local_g1_test_bench.u_g1_top.U_pim1_vhdl.U_g1_applic_top_vhdl.refclk_capt_tk ); 
    
       repeat(4)
         @(posedge u_local_g1_test_bench.u_g1_top.U_pim1_vhdl.i_clk);
       
       u_local_g1_test_bench.timestamp_sync = 1;
    
       // Wait for all transactors to finish
       fork
       // Wait for the aurora bus model to finish
       wait( u_local_g1_test_bench.AURORA_RX_DONE );
    
       // Now just wait for the signal from the ebc bus model.
       wait( u_local_g1_test_bench.EBC_DONE );
    
       wait( u_local_g1_test_bench.HOTLINK_DONE );
    
       join
    
       #10000; // Delay 1uS = 1,000,000 ps/100ps 
    
       u_sim_services.print_test_results;
    
       $finish;
    
    
    end
    
    endmodule
    The question is how do I receive or obtain this differential clock at local_g1_test_bench.sv?



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  4. #4
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    Re: Send one parameter from systemverilog to another in Vivado 2017.3

    Do you know how to
    Then use port mapping to transfer this diff clk from stimulus.sv to local_g1_test_bench.sv or other instances.
    ?

    You already have wire [3:0] pgm_user_clk_*. Just connect this to wherever it is needed!
    You can use plain, simple Verilog.

    Just have a similar dimension array in your test-bench sub-module as ports. Then port-map them.
    FPGA enthusiast!



  5. #5
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    Re: Send one parameter from systemverilog to another in Vivado 2017.3

    Thanks for the help ... tell them that I managed to solve my problem, where I only send the time parameter as follows.

    stimulus.sv
    Code:
    local_g1_test_bench #(.sim_pim1_uclk (2500)) u_local_g1_test_bench ();
    local_g1_test_bench.sv
    Code:
    module local_g1_test_bench();  
    parameter sim_pim1_uclk = 5000;
    
    reg sim_pim1_uclock0 = 1;//IEA Added
    reg sim_pim1_uclock1 = 1;//IEA Added  
    reg sim_pim1_uclock2 = 1;//IEA Added
    reg sim_pim1_uclock3 = 1;//IEA Added
      
    always//IEA Added
       #sim_pim1_uclk    sim_pim1_uclock0 = ~sim_pim1_uclock0; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #sim_pim1_uclk    sim_pim1_uclock1 = ~sim_pim1_uclock1; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #sim_pim1_uclk    sim_pim1_uclock2 = ~sim_pim1_uclock2; //  6.80 nS period 147.06 MHz NEW//IEA Added
    always//IEA Added
       #sim_pim1_uclk    sim_pim1_uclock3 = ~sim_pim1_uclock3; //  6.80 nS period 147.06 MHz NEW//IEA Added 
       
    //assign i_pim1_uclk_p =  {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
    //assign i_pim1_uclk_n = ~i_pim1_uclk_p;   
                   
    wire [3:0] pgm_user_clk_p = {sim_pim1_uclock3, sim_pim1_uclock2, sim_pim1_uclock1, sim_pim1_uclock0};
    wire [3:0] pgm_user_clk_n = ~pgm_user_clk_p;



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