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    Why not simulate ATPG pattern in ATPG TetraMAX tool

    hii,

    why requred to simulate atpg pattern in vcs but Synopsys Tetramax tool also option of run_simulation?

    Thanks,

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  2. #2
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    Re: Why not simulate ATPG pattern in ATPG TetraMAX tool

    If I understand your question framing correctly..........

    The Tetramax tool just generates the pattern which needs to be fed to your DUT and its behavior has to be observed.
    VCS is a simulator tool using which you can see how your logic components toggle when the patterns pass through the DUT.

    It has been a long time I have not used the tetramax and the vcs, but I think if the run_simulation is supported then this command can call the simulator. Here you can avoid manually calling the simulator/VCS. Please refer to the Tetramax command reference manual for details on how to do that.
    FPGA enthusiast!



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    Re: Why not simulate ATPG pattern in ATPG TetraMAX tool

    Thanks for give response,dpaul

    when I simulate in Tetramax tool using run_simulation then required to simulate in vcs or any difference between TetraMax and VCS pattern simulation.


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    Re: Why not simulate ATPG pattern in ATPG TetraMAX tool

    You are getting things wrong.
    You use the pattern generated by Tetramax to run simulation. VCS is just a simulation tool which uses this generated pattern and feeds them to your design. Use VCS for simulation.
    I think you should read the user guide thoroughly.
    FPGA enthusiast!


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    Re: Why not simulate ATPG pattern in ATPG TetraMAX tool

    run_simulation is based on internal fault simulation engine in tetramax. vcs simulation is to simulate the ATPG patterns agaisnt verilog behavioral models. The former has some use models, one of them is to test how much faults the patterns can test. The latter is to ensure patterns will work and pass finally on tester.



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