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Logic Buffer IC delay (74HC4049)

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treez

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Hi,.
The HC4049 buffer has a transition time of 19ns (at 4v5=vcc) and a propagation delay of 21ns. Does that mean a low to high transition will actually take 40ns?

74HC4049 datasheet
https://www.ti.com/lit/ds/symlink/cd74hc4049.pdf

Also, these timings relate to a 50pF load capacitance…but what if I am cascading them, and I only have therefore 10pF load capacitance…what then are the timings?
The output impedance isnt given, so i cant do an RC delay calculation.
 

You can refer to the typical propagation delay (6 ns) for a rough estimation. Adding transition and propagation or looking at maximum values doesn't a realistic picture.
 

right there on page 4 is a pretty picture explaining exactly what propagation delay and transition time are. Propagation delay is the time from the midpoint of the input transition to the midpoint of the output transition. I, personally, would design for worst case values. If you design for typical values, you're just asking for trouble.

Without further information about your circuit it's not possible to offer any more advice. But I have to ask why you would cascade these gates. Two inverters is exactly the same as no inverters.
 

I, personally, would design for worst case values. If you design for typical values, you're just asking for trouble.
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Normally yes. treez is however designing logic gate delay. It should start with typical values, considering the full min to max range.
 
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