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Negative power supply delay in bias sequencing circuit

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caoquyen164

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Hi all,
I'm designing a bias sequence circuit for GaN Power Amplifier, the same as "AN11130-Bias module for 50 V GaN demonstration boards".
the problem is in the off-state. the gate voltage should be goes from -5 to 0 after the drain voltage goes down to zero. It can be fine if I insert a control signal to turn off Vdrain then turn off the Vgate. but in the case the power/battery is shut down suddently, the thing will go bad, the PA IC may be damaged.
I need to extend the life time of -5V power line about 100ms after the power supply is shut down suddently. I tried to insert a RC delay or a large capacitor in -5V line, but they do not work. can anybody help me ? tks.
20191212.jpg
 

Appears that both supplies have an externally asserted,
hard turnoff (maybe the battery-drop, but maybe some
other "feature" of the power supply controller(s).

A question right off the top is, when you add the "large
capacitor" does the discharge ramp look like
dV/dt=Ioperating/Cbigfat, or is it getting jammed to ground
by some external, much lower, impedance? If this is the
case then maybe you need not just a hold-up capacitor
but a smart disconnect from the shunting device and
supply, until your own discharge at your own chosen time.
Like a negative load switch that "opens" when battery has
gone out, before converter UVLO has been hit to initiate
the discharge itself (if that's the chain of events).
 
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