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  1. #1
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    How hold violation caused by below mentioned Scenceio

    Hi All
    In my design D is changing just before clock edge but there were no violation reported. I know it is because of massive hold violation because launch clock is coming early and capture clock is coming because of which data slippage is happening. Can anyone help me what exactly happening here. Also why can't it be setup violation?

    Thanks and Regards.,
    Varun Kumar M S

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  2. #2
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    barry's Avatar
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    Re: How hold violation caused by below mentioned Scenceio

    How about a diagram? Your description is very confusing.



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  3. #3
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    Re: How hold violation caused by below mentioned Scenceio

    1. Have you simulation run considering min corner or max corner SDFs?
    2. Do you see the failures or mismatches during 0-delay sim on the same register you are talking about?



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