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    Designing of high GBW opamp

    Dear friends,

    I am trying to design a floded cascode OTA for the sample and hold circuit that should work with sampling frequency of 5 MHz, this requires me to have an OTA with a typical GBW of 100 MHz. I am using 0.35 um CMOS technology with channel length I st for all the transistors to 1 um.

    The problem I am finding it very difficuilt to achieve this GBW, I am using 120 uA for biasing my differential pairs with W/L = 60 (PMOS type )

    I am thinking if I reduce the channel length I should expect a wider GBW, is it could method ? what is the typical minimum length I should use in my technology to keep other OTA properties as well ?

    Thanks

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    Re: Designing of high GBW opamp

    You speak of reducing "the" channel length, but this is not
    something you should treat as a "single setting". Different
    functions may likely want different geometries.

    For a load you might prefer a longer channel to raise Rout
    up to where it doesn't "contribute" to gain-node impedance
    (parallel diff pair Rout, load Rout, next stage Rin) as its gm
    is a don't-care.

    In the diff pair, you are in a foot-race between increasing
    gm and decreasing Rout, for gain as you reduce L. The
    BW will benefit, gain may or may not.

    For high BW you may have to step away from low power
    DC amplifier topologies, more gain stages at lower gain
    apiece. This will be harder to compensate and despite
    higher bandwidth, settling time might be same or worse.
    OTAs are inherently easy to compensate (shunt C at
    output) but not great performers especially as large
    hold capacitor drivers. If Chold >> Ccomp_min, that's a
    soggy amplifier (but dead stable). You might like to run
    the amplifier "so hot that Chold == Ccomp" for whatever
    Chold needs to be, for the sample to stay right across
    the conversion cycle. Might need to work backwards from
    that (hold attributes) to amplifier particulars?

    Here's a basic question. Are you really needing an amp,
    or would a simple sampling switch do the job? That all
    comes down to the signal source impedance coming in,
    and what the driven load needs for input. If it's a
    50-ohm system then maybe you just switch, to sample,
    and let (Rsrc+Rsw)*Chold define the settling time (how
    many tau, to what number of bits...). This is system
    specific, a "general purpose" architecture might need
    to accommodate a range of source impedances. But
    beware the engineer's impulse to make a general
    solution to a specific problem, and if it's a specific
    application and only that, look for simple solutions
    before you make a complex project out of it?


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    Re: Designing of high GBW opamp

    Wow, you have a sampling frequency of 5MHz, which means you have to settle within 50ns while tracking the signal (say Ts/4 for slewing and another Ts/4 for linear settling, Ts is sampling clock period). But you want a GBW=100MHz which will make a time-constant of 1.6ns. So, your time for settling is 30x longer than the time-constant. How about you leave something like 10 time-constants, instead of 30 - this will mean you settle to a 10 bit accuracy. In this case 50ns/10=5ns for your OTA timeconstant, which is GBW=30MHz instead of 100MHz. What is your settling precision accuracy?


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  4. #4
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    Re: Designing of high GBW opamp

    Quote Originally Posted by dick_freebird View Post
    You speak of reducing "the" channel length, but this is not
    something you should treat as a "single setting". Different
    functions may likely want different geometries.

    For a load you might prefer a longer channel to raise Rout
    up to where it doesn't "contribute" to gain-node impedance
    (parallel diff pair Rout, load Rout, next stage Rin) as its gm
    is a don't-care.

    In the diff pair, you are in a foot-race between increasing
    gm and decreasing Rout, for gain as you reduce L. The
    BW will benefit, gain may or may not.

    For high BW you may have to step away from low power
    DC amplifier topologies, more gain stages at lower gain
    apiece. This will be harder to compensate and despite
    higher bandwidth, settling time might be same or worse.
    OTAs are inherently easy to compensate (shunt C at
    output) but not great performers especially as large
    hold capacitor drivers. If Chold >> Ccomp_min, that's a
    soggy amplifier (but dead stable). You might like to run
    the amplifier "so hot that Chold == Ccomp" for whatever
    Chold needs to be, for the sample to stay right across
    the conversion cycle. Might need to work backwards from
    that (hold attributes) to amplifier particulars?

    Here's a basic question. Are you really needing an amp,
    or would a simple sampling switch do the job? That all
    comes down to the signal source impedance coming in,
    and what the driven load needs for input. If it's a
    50-ohm system then maybe you just switch, to sample,
    and let (Rsrc+Rsw)*Chold define the settling time (how
    many tau, to what number of bits...). This is system
    specific, a "general purpose" architecture might need
    to accommodate a range of source impedances. But
    beware the engineer's impulse to make a general
    solution to a specific problem, and if it's a specific
    application and only that, look for simple solutions
    before you make a complex project out of it?
    Dear free_bird,

    Thank you very much for your nice explanation, you are right, not every transistor contribute to the speed, so only these transistors that contribute to the non-dominant pole needs to be reduced, the load and the mirror transistors has to keep for them long channel for better matching and higher resistance for gain

    - - - Updated - - -

    Quote Originally Posted by sutapanaki View Post
    Wow, you have a sampling frequency of 5MHz, which means you have to settle within 50ns while tracking the signal (say Ts/4 for slewing and another Ts/4 for linear settling, Ts is sampling clock period). But you want a GBW=100MHz which will make a time-constant of 1.6ns. So, your time for settling is 30x longer than the time-constant. How about you leave something like 10 time-constants, instead of 30 - this will mean you settle to a 10 bit accuracy. In this case 50ns/10=5ns for your OTA timeconstant, which is GBW=30MHz instead of 100MHz. What is your settling precision accuracy?
    Dear Suta,

    Thank you for the reply

    I need to work with 12 bit pipeline ADC,

    I didn't go to the details of the sample and hold but what you presented is very useful information, could you please give me the source text of so I can read more details ?

    - - - Updated - - -

    Dear Suta, I forgot to ask you how you are calculating the time settling from the GBW of the ampliifer ?



  5. #5
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    Re: Designing of high GBW opamp

    You have an OTA with a feedback. The GBW is the frequency where the loop gain crosses 0dB. The same GBW frequency is the -3dB frequency of the closed loop amplifier (assuming a 1st order loop gain response). The reciprocal of the -3dB frequency (in rad/sec) of any 1st order system is its timeconstant. So, 1/GBW is the timeconstant of your closed loop OTA.
    BTW, I said wrongly in my previous message that you need 10 time-constant for 10 bit accuracy. For 10 bits you need something like 7.6 time-constants to settle to half a bit. The number I gave you, i.e. 10 time-constants is more suitable for 12 bit accuracy for settling within half a bit. I guess, you can always make a simple OTA model with your targeted -3db frequency (or GBW), give it a step and see how long it takes to settle to about half a bit at the 12 bit accuracy.


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