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  1. #1
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    Timing ARC for Asynchronous Signal

    Hi All,
    I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??

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  2. #2
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    Re: Timing ARC for Asynchronous Signal

    Quote Originally Posted by Varun124 View Post
    Hi All,
    I have some doubt regarding timing arc. What is timing arcs. Is there any hardcore rule that if any port is asynchronous signal then it should have timing arc??
    unclear. are you talking about timing arcs within a standard cell or within a design?
    Really, I am not Sam.



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  3. #3
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    Re: Timing ARC for Asynchronous Signal

    Yes within stand cells



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  4. #4
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    Re: Timing ARC for Asynchronous Signal

    the rule is simple: any input that causes a change to an output is considered during std cell characterization. the tools that are farther up in the implementation chain need to know the delay and power consumption associated with a toggle on the input.
    Really, I am not Sam.



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