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  1. #1
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    Latchup Caused by diodes

    Hi,
    I've searched through here and on google but haven't found anything about this.
    Typically, latchup is illustrated with nmos and pmos. The SCR is drawn based on those two devices. Is that to say that if the pmos was a p-diode or the nmos was replaced by an n-diode, there would be no latchup concerns? The question comes from some tests I've put together:
    I can generate LU errors with nmos and pmos but if either of the nmos or pmos is replaced with a diode, LU errors desappear. Confusing because there's still a thyristor whether we have nmos/pmos combination or nmos/p-diode or pmos/ndiode combinations.

    An input would be appreciated.

    Thanks

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  2. #2
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    Re: Latchup Caused by diodes

    A thyristor can be modelled as two transistors that keep each other saturated. This can't happen if you replace one of the transistors with a diode.
    A thyristor is not an arbitrary PNPN structure. If it was that simple, you could create a thyristor by connecting two normal diodes in series.



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  3. #3
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    Re: Latchup Caused by diodes

    NMOS and PMOS are your explicit, desired devices. Each
    has parasitic BJT "baggage". Thie baggage forms numerous
    SCR structures throughout the chip and each one needs
    to have a wide enough base and a stiff enough base-
    emitter shunt, that SCR triggering won't happen and
    holding will quench.

    NMOS forms lateral NPNs to NWell and other NMOS. PMOS
    in NWell is a substrate PNP, and the PMOS also have lateral
    BJTs within Nwell. Any two N features in psubstrate make
    lateral NPN - FET or diode, no different.

    There are many good latchup tutorials and presentations.
    If you aren't finding them on Google, you aren't googling
    very hard. One good cross section cartoon ought to show
    the mechanisms and key features in a useful way. Try
    "CMOS latchup" and look at the pictures.



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