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Reducing leakage by applying negative Vgs (NMOS)

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komax

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Is it possible to reduce leakage current by applying Vgs=negative (NMOS transistor) instead of Vgs=0? I notice in my simulation that at negative Vgs the leakage current is lower and it is proportionally lower the more negative the Vgs.

What is the relationship between leakage current & Vgs (negative)? Are there plot or formula I can look into for this region?

Thanks!
 

This works, to a point. However, there is a phenomenon
known as GIDL (gate induced drain leakage) which will
eventually cause the leakage floor to rise back up from
its minimum, as you further drive the gate voltage
negative. This is technology-specific and length-variable.
Simulation models may or may not have been made to fit,
depending on things like the anticipated applications of
the technology (in digital, how often is gate ever taken
below vss?) or the modeling person's attention to detail
and workload.
 

Thanks for the answer.

Reliance on simulation models were exactly my next thoughts/questions on the subject. I am currently designing a circuit that has negative Vgs and it's critical that the leakage amount is reduced according to what the models say in simulation but to what extent can I trust that the models are correct and the silicon will behave the same way? Are there any simple calculation that I can perform to double check?

The models themselves come from the foundry so I think it's reliable right?
 

You want real device measurements, calculations are only
as good as the data, assumption, simplifications behind
them.

I've been inside foundry and I've been fabless and the only
thing that makes sense to me is "trust noone". Especially
when you're stepping off the beaten path. If you can find a
"model vs WAT" report but in it, can't find anything showing
negative Vgs, then don't trust that the models match the
silicon. If you can't get the report, then don't trust the
organization.
 

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