Average vs RMS load-current for LDO design

[komax]

I am designing an LDO that will be used to power a small digital circuit. I have access to said digital circuit and have been simulating my LDO with it.

My question: when designing my pass device to support maximum load current, which numbers should I use, average or RMS current? And why?

Follow up question: when measuring the load current I realise that the current goes both ways (+ and -), so if I were to measure RMS the negative current will be squared and counted as well while in reality this negative current simply represents kick back current towards the LDO due to switching (I think), wouldn't counting these current be over-design? Should I make some adjustment to the waveform to get rid of negative parts before taking RMS then?

Thank you in advance for your kind help.

[c_mitra]

when measuring the load current I realise that the current goes both ways (+ and -),..

It is surprising; a small digital circuit as a load to a LDO regulator is not expected to act like this! Can you please provide more details?

[KlausST]

Hi,

My question: when designing my pass device to support maximum load current, which numbers should I use, average or RMS current? And why?

* For devices where the voltage (across it´s pins) is directly proportional (like a resistor): use RMS
* for devices with about constant voltage (across it´s pins), independent of current (like diodes, LEDs): use AVG.

...in most cases. It depends what you want to calculate

Klaus

[komax]

It is surprising; a small digital circuit as a load to a LDO regulator is not expected to act like this! Can you please provide more details?

It's actually 10x of the same digital circuit, so in total they are not so small I guess. The range of RMS current I'm getting is 2.5mA typical and 5mA worst case.
The circuit itself is a driver circuit that is switching at 200MHz, I didn't dig deeper on what else are inside.

[komax]

Thanks for the reply.
How about if I want to calculate the current consumption of a switching digital blocks, do I use RMS or AVG?

Basically I want to make sure that I design the size of my pass device sufficiently to support the digital circuit while it's switching at its highest frequency and heaviest activities. I have the waveform of this current (kind look like noise with peaks here and there, e.g. 5mA peak, 10mA, etc), I'm wondering if I should calculate RMS or AVG for designing the LDO's pass device.

[crutschow]

For a DC current, the average and the RMS are the same.

[KlausST]

Hi,

How about if I want to calculate the current consumption of a switching digital blocks, do I use RMS or AVG?

This s a vague question, thus I can´t answer it.

A digital block has several units inside.. Show us a setch of your "building block" and show what voltage and what current you want to use for power calculations.

If you have the sketch you should easily find out by yourself whether V and I are in a proportional relationship or not.

Klaus

[c_mitra]

For a DC current, the average and the RMS are the same.

Not correct. This is true only for a constant current.

I guess I need not elaborate.

[KlausST]

Hi,

Not correct. This is true only for a constant current.

I guess I need not elaborate.

When I think about DC current, then it´s a straight horizontal line. Thus in my eyes every DC current is constant.

****
But maybe you see "DC" as every signal that just does not go negative. Then you are correct.


Klaus

[c_mitra]

When I think about DC current, then it´s a straight horizontal line...

In that case, the rectified output of an AC is not DC; but I am not sure what is the more common understanding.

[wwfeldman]

I would size this LDO pass element depending on desired Vout, say 5V, drop out voltage, say 1V, so i need at least 6 V in
the current requirement has to be the maximum current the load will draw. plus a little margin
what is the actual input voltage?

your device is drawing, ??? per digital circuit at its highest frequency? (let's say 5 mA for fun)
multiply that by 10, unless you can guarantee the maximum number of your digital circuits that may be"ON" at the same time is less than 10
(or 50 mA)

and add about 10 to 20% margin. (60 mA)

since you now know current and voltage, find power and add a heat sink.

so this (hypothetical) LDO pass element will drop 1 V at 60 mA, or 60 mW
your device will drop the maximum voltage across the pass element times the maximum current (worst case - so design for it)

check the LDO specs to size capacitors on input and output, especially if you need to pick so it doesn't oscillate

[FvM]

For a DC current, the average and the RMS are the same.

Not for pulsed DC. But that's just theory and doesn't actually matter for the question.

The voltage regulator power dissipation only depends on the average DC current, the circuit must be additionally able to provide expectable peak current. No need to measure or calculate RMS numbers.

The circuit itself is a driver circuit that is switching at 200MHz.

Do you actually expect 200 MHz current components loading the power supply? Did you forget to install bypass capacitors in your circuit?

[frankrose]

How about if I want to calculate the current consumption of a switching digital blocks, do I use RMS or AVG?

Basically I want to make sure that I design the size of my pass device sufficiently to support the digital circuit while it's switching at its highest frequency and heaviest activities. I have the waveform of this current (kind look like noise with peaks here and there, e.g. 5mA peak, 10mA, etc), I'm wondering if I should calculate RMS or AVG for designing the LDO's pass device.

Hi,

Use RMS. It is the most talkative to estimate the load current with its all DC and AC components, and some overdesign is still necessary.
For example the voltage ripple on your LDO output should be low as possible, and probably design only for nominal current consumption is not enough to keep ripple low.
Bypass capacitor is not a solution always. Big load capacitance (even nF capacitors) can cause stability issues at certain LDOs, however to handle very fast peaks like in your case some capacitance (pF range) at the output is recommended.
If you design integrated circuit also necessary to know the AVG and PEAK values. Electromigration checker use different rule constants for those.
If it is not integrated I still suggest to calculate/measure AVG and PEAK values too, obviously they can tell you more info about your circuit.

[KlausST]

Hi,

I don't agree.
One should not mix RMS and AVG.
Each value makes sense, but one value can not replace the other.

One application where one can see the difference is the power dissipation calculation of SCRs.
(If interested, read some application notes about this topic.)
At SCRs there is a combination of two major power dissipation sources:
* one is the diode drop where you need to use AVG current
* and the other is the ohmic power dissipation, where you need to use RMS.
Both calculated values combine to the total power dissipation.
--> you can not use RMS only and you can not use AVG only.

Klaus

[frankrose]

Digital load current is like noise, as described in #5, and noise is characterized with its RMS value.
I agree with the difference, but SCR example is misleading now I think, or maybe it is answer for an other post.

[KlausST]

Hi,

I see your point.

But I also see that the OP asks about LDO dimensioning and load current.
And when I hear "power supply" I see a constant input voltage, whare a "squared value" makes no sense.

As already written in post #3v

...in most cases. It depends what you want to calculate

And the requested sketch ( in post#7) can clarify this.

Without exactly knowing what the OP really wants to calculate I can't give no detailed answer.

Klaus

[FvM]

LDO pass transistor power dissipation is (Vin-Vout)*avg(Iout). Additional considerations for SOA. Irms isn't present in the calculations.

[KlausST]

Hi,

This is exactly my idea, too (without more information from the OP)

Klaus

[komax]

Hi,

This is exactly my idea, too (without more information from the OP)

Klaus

Sorry for the late reply, just hit morning here.

This illustrate what I want to do: Vout vs Iload

In the X-axis is a sweep of load DC current of the LDO, on the Y-axis is the LDO output. In this example I can see that 5mA is the maximum limit for my LDO and thus it can safely support any load up to that point.

My question is when I am given a digital blocks to design the LDO for, how do I approximate the equivalent DC current that I need to support based on the current waveform of said digital block. In other words, what is my "5mA" in that picture if I have the load current waveform, should it be based on average or rms?

The digital blocks themselves are a bunch of digital gates and inverters, so I don't think the V and I are proportional like resistor.

[crutschow]

LDO pass transistor power dissipation is (Vin-Vout)*avg(Iout). Additional considerations for SOA. Irms isn't present in the calculations.

As I stated, for a steady DC output, such as from a linear regulator, the average current is the same as the RMS current (for DC the RMS calculation is trivial).