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  1. #1
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    Low power optimization problem in competitive vendor economics

    Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power

    Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if i choose to replicate nop type power reduction scheme. not only would an copy be slow, it would also consume more power from replication of N number of nops.

    Several schemes use survival of fittest logic( just psychology to choose winner), for example: Michael hsiao, sequential atpg using hadamard, Niermannn's hitec.


    -suresh

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  2. #2
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    Re: Low power optimization problem in competitive vendor economics

    Hi,
    If you want a detailed answer yo need to give detailed informations first.
    You now just give vague informations as if you are talking about a top secret application.

    Every microcontroller manufacturer provides power saving informations in the datasheet and application notes.
    Never heard that NOP is used for power saving. But usually there are various sleep modes...

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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  3. #3
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    Re: Low power optimization problem in competitive vendor economics

    Quote Originally Posted by firewireblue View Post
    Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems.
    this makes no sense.
    Really, I am not Sam.



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