Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Low power optimization problem in competitive vendor economics

Status
Not open for further replies.
F

firewireblue

Newbie level 4
Joined
Nov 29, 2019
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
74
Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power

Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if i choose to replicate nop type power reduction scheme. not only would an copy be slow, it would also consume more power from replication of N number of nops.

Several schemes use survival of fittest logic( just psychology to choose winner), for example: Michael hsiao, sequential atpg using hadamard, Niermannn's hitec.


-suresh
 

Hi,
If you want a detailed answer yo need to give detailed informations first.
You now just give vague informations as if you are talking about a top secret application.

Every microcontroller manufacturer provides power saving informations in the datasheet and application notes.
Never heard that NOP is used for power saving. But usually there are various sleep modes...

Klaus
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top