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Flyback controller explain

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95% of the time when the converter works without the problem, the output voltage build ok, and without falling at the steady-state.
in the other 5% of the time output voltage not build at all. because of the OC protection that triggered for some reason (the problem).
 

Are the cores moving in the Tx? what is the gap you have used? how slow is the soft start?
 

I dont, how i know if there is something wrong with the phasing?

if you are asking this sort of question - you are going to have real trouble getting this ckt going ...
 

benjal...to find phasing...you assign a dot to one end of one coil (call it coil A)...you then measure inductance of coil A......then you connect that coil A in series with another of the coils (coilB).......and measure the inductance of coil A and coil B in series.....if the inductance value is LESS than what you got for coil A alone, then you have connected the coils dot-to-dot......(or no_dot-to-no_dot if you like)

I am sure you now understand how you now can do phasing for all the coils....

The principle is based on field cancellation, or field enhancement...depending on whichever way you connect them....and hence you can get where the dots are

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Has your converter ever worked and given correct vout on each output when they were all on max load?

If not, then remove all output diodes accept the one on the 3.3v rail that you are bringing the regulation off.......use a dummy load and get it working with that rail alone first.
Maybe you also remove some of the output capacitors from that rail so it can get up into regulation sooner....then we go from there, when you have something working.

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Also, what is the part number of your D16 (?) (output diode of 3v3 rail) it looks like "PDSS10CH-13"....am i correct?

By the way, you probably need rc dampers across the output diodes...and have you interleave wound the transformer?
If not, see AN18 from powerint.com

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Also, what are the max loads on each output?

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I have put your flyback into LTspice simulator and attach it here…I guessed your power is 20w for the 3v3 rail and only included that one.
If you give more detail we can get it better.
Just open it in the free ltspice but first change the .txt to .asc
I added some other bits of filtration, eg the 150pf offered by EasyPeasy, and some others.
 

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    Flyback Benjal in LTspice.jpg
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treez, Thank you very much for your reply, I don't think that phasing is the problem because the circuit works fine at 95% of the cards, and each card is the same circuit with the same load.

Moreover when I changed the limit of 15A to 25A at the Overcurrent its work fine even at bad cards (the other 5%).
so the problem is not Permanent but only at the beginning.
what I ask is simple, I don't want to change the limit, but I can't understand why at 95% the times the current at the beginning burst is about 10A and in other cases came up to 22A.

thanks for help,
 

15A to 25A at the Overcurrent
Your sense resistor is too big (high Ohms) to allow 15A to flow.
Whan you say "Overcurrent", do you refer to the OC pin on the LT3805?
You do need a filter capacitor on that OC pin...like i have added on ther simulation.

You say some cards work and some dont.......maybe the working ones had the input capacitors already pre-charged.

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You seem to be hinting at "intermittent bad operation".
You seem to be saying that 95% of the PCBs with this power supply on work fine, but the others dont?

As far as i am concerned, your schem from the top post is poor in terms of not having capacitors on the OC pin, and on the Isense pin.

None of us here can really judge your schem though because you do not give the loading on each secondary.

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You seem to repeatedly say that the OC trip is whats bothering you.......you need to put a capacitor on the OC pin, as i have done in the sim....i have no idea if your OC trip point is set properly...and i cant work it out, because i dont know what is your loading?
Is it that you dont really know what the maximum load is?...

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Before designing such a power supply, it is always best to get a representative simulation of it working first, then go to the bench. Simulations aren’t that useful…but if you cant get some kind of representative simulation working first, then you will generally never get the real thing working.
There is the LTspice simulator which has a model for your LT3805, and so you should be able to get a very representative simulation working first.
I cannot do the simulation for you because I don’t know the loading on each of your secondarys.

I have requested from yourself the loading, but you do not tell it.....is this becausue this is someone else's power supply that you have had dumped upon yourself, and you dont know the spec?

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So anyway, it sounds like your OC pin is getting tripped, and this may be due to the lack of an OC pin capacitor. And/Or maybe there is too much capacitance on the secondaries and it cant start up without tripping OC…..only 5% fail because maybe there is a tolerance on OC trip point, or whatever, and those 5% fail that tolerance.
If you wanted to be really naughty, but cut to the chase, you could just ground the OC pin and see if it starts up then (the bad ones)
 

Yes, when I say overcurrent I mean that the OC has been triggered.
I did put a 1nF filter capacitor on the OC pin like you said and don't have any difference.

well, the bad/good cards they both starting with the same condition (after a long break).
like I said before, 95% of the cards works fine, the other 5% - the same circuit doesn't start-up. when I check the primary current at the first burst I see (at the 95% cards) ramp until about 10-12A.
and for the "bad" it enters to hiccup mode (OC triggered due to high current - on my circuit the limit is 15A).

the simulation works fine so it can't help me.
yes, this is someone else converter design and I worked on the converter to fix the problem.

in addition to 5% of the cards when I replace the controller with another problem solve.
and to the 5% when I increase the limit (change the resistors on the OC) the problem also solve. (but still, I getting burst up to 20A - which I don't want).

I attached the secondary circuit.
again, thank you very much for your help!


5.PNG
 

So I think we agree that there is too much capacitance on the secondaries, and sometimes, depending on tolerance in the LTC3805, this trips the OC .
….and it goes into hiccup mode.
As you discuss, your primary current staircases up to 20A during the startup…..by the way, what is the voltage on the drain of the primary FET when the 20A peak current is there?......your RCD clamp circuit may be getting well overcharged by such an intense startup transient, and maybe your FET is getting overvoltaged and avalanching.
I think there is two ways to deal with it.
1…..reduce capacitance on secondaries till problem goes.
2…..Dont have any load on the secondaries until they get up to voltage….then you will find they eventually get up to ovoltage after a few timeouts....to reduce the 20A...reduce the OC trippoint,,,,,it will mean more timeouts, but it'll get there in the end.


(BTW i see some 10 secondaries there, do you really have that many.?..and what is the power on each one?)
 
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this is why the soft start should be set to several seconds - to allow the charge up of the sec side caps without tripping the peak current sense - set much earlier posts on same topic
 
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In addition, datasheet specifications are made with some percentage of confidence - 90%, 95%, or so.

Having 5% of the cards fail depicts a choice that have been made by the designer on a parameter that may have been specified with 95% confidence. If your converter is experiencing hiccup, it could be that the converter is overloaded just like I had mentioned in a previous post.

Typical example is when maximum duty cycle is specified in the datasheet. The specified maximum duty cycle has minimum, typical and maximum values. The typical value that is specified is with a certain level of confidence which is lower than 100% and so the design might experience defects of (100 - confidence_level)% if the typical value is used. The best bet is for the designer not to design for a duty cycle that is higher than minimum specified range, else the duty cycle might saturate. Saturated duty cycle can cause hiccup.

Choice of use of typical values are very okay for certain parameters but not okay for certain others and a careful consideration is required when making these choices.
 
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If there’s too much capacitance, then even a long soft start won’t stop it from tripping out on the OC pin.
Go to extremes, imagine an infinite capacitance on the output…its voltage won’t rise….the soft start hampered reference voltage will slowly build, but eventually will get high, and the primary current will staircase and eventually trigger the OC threshold. For the first 6% of the cycle time, the “isense” current limit does not operate….(for LEB purposes).
If your capacitance is above this value, whatever that is, then you will just have to tolerate timeout and restart and keep the output no loaded till you're up into regulation. If you are staircasing too high and your output capacitance is above the “too high” value, then you have to come up with a different solution….but really, surely you can set the OC point to an acceptable value,.,…..and then you just have to tolerate the multiple restarts until you are up into regulation.

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remember also that your effective capacitance value has to be gotten by referring all the separate secondarys' capacitances to your chosen main secondary.....so they need adjustment by the turns ratio.
 

If there’s too much capacitance, then even a long soft start won’t stop it from tripping out on the OC pin.

respectfully - this is not quite correct - we have have PI designs given to us that were in the same problem - we gave them a longer soft start ( sometimes called a soft finish in their literature ) - 1sec - 5 sec and they started ...

The current may not staircase to if the soft start is long enough - i.e. the duty cycle is kept low enough

For infinite capacitance you are stuffed - but that is not the case ...

Since you have post filters you can reduce all the capacitances to the min levels that are acceptable for ripple

Also you can re-design the Tx so the nominal Bpk is 100mT say - this will let you get to 320mT without saturation and OCD trip

you can also voltage divide the current signal at startup for a few secs so that the trip is 3x usual ...
 
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the simulation works fine so it can't help me.
yes, the simulation of post #14 does indeed work fine, and i am sure you woudl agree that this is because it doesnt have all your output capacitance in it.

The OC trip feature, and timout feature are probably incorporated in the LTspice model for LTC3805, so why dont you complete the schematic for the simulation, and then re-run it.
Having said that, with all that capacitance, it may take some time to run...and if you include the leakage factor in the transformer, it may take much longer still.

Why not refer all your output caps to the one main secondary, (remember to use the turns ratio to refer the caps) and then try the sim like that?...ie just using the one secondary in the sim...the regulated secondary.
Set the OC point accordingly......give it a decent margin, becausue you already see that there is tolerance since 5% of your boards fail.....so account for this by setting OC point and soft start appropriately...give it decent margin to disallow the poorly toleranced to spoil the day, as they are currently doing in your 5% of badboys.

...And use the "soft Finish" circuit, or the extended soft start circuit, as recomended by Easy Peasy. The simulator can do that for you.
As you know, you will have to verify it with the hardware, but it can be quicker "to get into the ball park" first by using the simulator.


The one thing, if you set OC trip low enough then its no great disaster....because you can have all your secondaries no-loaded, and then just suffer several timeouts and restarts before you get up into regulation....but you dont like this idea?
 
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I think that with any converter, (lets talk flyback for now) if you have above a “certain amount of output capacitance” on it, then eventually you end up with a situation where your vout simply isn’t building up quickly enough at start-up…and it stays very low for long periods. As you keep switching the FET , so flux builds up in the core, and the vout isn’t enough to discharge the secondary sufficiently….so you end up with staircasing of the primary current……….as you know , we cannot expect to just switch the fet on for a very low duty cycle because the minimum on time means that we always have the FET on for that minimum time. The result is that if the vout just doesn’t build up quickly enough, then the primary current will staircase upward and we will trip the OC point (in the case of LTC3805)
Especially in cases where there is also a loading on the converter at startup, loading it even when the vout is very low…then your vout will just not build up quickly enough during the soft start, and staircasing will result…which will eventually result in overcurrent trip in the case of LTC3805.
I appreciate that soft finish circuits and extended soft starts do extend the amount of output capacitance that can be handled…but if you keep increasing output capacitance, higher and higher…then you eventually get to a point where you are going to end up staircasing and tripping the OC trip point (or tripping the timeout feature in the cases of offline flyback chips) ….and you cant solve it with soft finish or extended soft start circuits….because they, by their nature, start off by having a low amount of power throughput, which in turn means the vout on the output capacitance just wont build up quickly enough…especially if there is loading on the output aswell.
I worked at one place where there was an enormous capacitor on the output of a flyback (to allow the product to be powered for a good time in the event of mains failure). They tried soft finish and extended soft starts, but couldn’t stop it from tripping the control chip’s timeout feature…and because the secondary was also loaded…they couldn’t even get the vout up after a few timeout-and-restarts….so they ended up switching the load off during start up…and then the device eventually charged up the output caps after a few “hiccups”.

Here is a soft finish
**broken link removed**

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Also, from knowledge of some India designs, where there are often power cuts in places, i remember there were often quite enormously huge amounts of output capacitance used.

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I worked in another place where (with an offline flyback) they had an enormous flash capacitor…and they couldnt have too much soft start as they needed to charge it up within a certain time….so they put diodes in series with the output capacitor so that there was initially some voltage to discharge the flyback secondary……they were using a Boundary mode flyback chip…so they actually wont staircase because the chip waits for the secondary to fully discharge before the primary switchs back on again….however, they also have a maximum OFF time….and if the vout doesn’t rise quickly enough, then it exceeds the maximum off time, and so in that case you can indeed get staircasing…hence they added the diodes in series with the flash capacitor.

As such, i think Benjal may indeed need to reduce the output capacitance....or just no-load it till its in regulation and put up with a few timout-and-restarts
 

only the flyback has this limitation - any type of forward converter does not ...
 
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