NikosTS
Advanced Member level 4
Hello all,
I am instantiating an nport inside a VerilogA module and I map the pins of the module to the corresponding ports.
The nport is reading an .s2p file that has been produced from the SP analysis of a schematic ( a filter ).
I am adding the file as input to the nport and then use SP analysis, expecting the get exactly the same results as the ones of the schematic simulation.
However, the results are not correct :
1) It seems like the information of the output impedance is lost when I am mapping the ports because when I add a load at the output the S21 parameter doesn't change at all.
2) S22 parameter also gives a constant 0 db which of course is not the case.
I suspect that the mapping of the ports of the nport instance to the module's pins is implemented by an ideal VCVS (??) resulting in 0 output impedance.
Anyone has encountered something like that or has any suggestions?
I am instantiating an nport inside a VerilogA module and I map the pins of the module to the corresponding ports.
The nport is reading an .s2p file that has been produced from the SP analysis of a schematic ( a filter ).
I am adding the file as input to the nport and then use SP analysis, expecting the get exactly the same results as the ones of the schematic simulation.
However, the results are not correct :
1) It seems like the information of the output impedance is lost when I am mapping the ports because when I add a load at the output the S21 parameter doesn't change at all.
2) S22 parameter also gives a constant 0 db which of course is not the case.
I suspect that the mapping of the ports of the nport instance to the module's pins is implemented by an ideal VCVS (??) resulting in 0 output impedance.
Anyone has encountered something like that or has any suggestions?