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nport primitive and VerilogA

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NikosTS

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Hello all,
I am instantiating an nport inside a VerilogA module and I map the pins of the module to the corresponding ports.
The nport is reading an .s2p file that has been produced from the SP analysis of a schematic ( a filter ).
I am adding the file as input to the nport and then use SP analysis, expecting the get exactly the same results as the ones of the schematic simulation.
However, the results are not correct :
1) It seems like the information of the output impedance is lost when I am mapping the ports because when I add a load at the output the S21 parameter doesn't change at all.
2) S22 parameter also gives a constant 0 db which of course is not the case.

I suspect that the mapping of the ports of the nport instance to the module's pins is implemented by an ideal VCVS (??) resulting in 0 output impedance.
Anyone has encountered something like that or has any suggestions?
 

I suspect that the mapping of the ports of the nport instance to the module's pins is implemented by an ideal VCVS (??) resulting in 0 output impedance.
No.

Simply you have mistakes in Verilog-A code or/and Netlist.

Show me both Verilog-A code and Netlist.

Show me header of your *.s2p.
 
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No.

Simply you have mistakes in Verilog-A code or/and Netlist.

Show me both Verilog-A code and Netlist.

Show me header of your *.s2p.

You are right, if I map the ports to the pins of the module I get the correct S params.
The thing is that I need to map the ports firstly in some internal nodes ,which will be the inputs of a polynomial and the output of the polynomial will be the final output ( I am attaching a screenshot of the VerilogA code):
veriloga_code.jpg

In that way I am trying to model the nonlinearities of the actual circuit
 

Simply you can not understand S-parameter at all.

You ignore current. It results in ignorering impedance.
Can you understand energy conservative model and signal flow model ?
 

Simply you can not understand S-parameter at all.

You ignore current. It results in ignorering impedance.
Can you understand energy conservative model and signal flow model ?

So I have to specify output impedance and the output voltage be expressed as the output current flowing through that output impedance?
 

So I have to specify output impedance and the output voltage be expressed as the output current flowing through that output impedance?
No.
Surely learn a definition of S-parameters.

You have to calculate a1,a2,b1,b2 from s11,s12,s21,s22.
That’s all.

It seems you can not understand S-parameter at all as same as many people in this forum.
So you must not use a formulation based on S-parameters.
 
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No.
Surely learn a definition of S-parameters.

You have to calculate a1,a2,b1,b2 from s11,s12,s21,s22.
That’s all.

It seems you can not understand S-parameter at all as same as many people in this forum.
So you must not use a formulation based on S-parameters.

Can you be a bit more specific about the calculation of a1,a2,b1,b2 and how will that help me?

I would also prefer not to use S params but there is no other way as far as I know to properly model my schematic.
If you know any other way, feel free to suggest
 

Surely understand nport.
nport can work as any of Z,Y,H,F,S matrix even if file of nport is S-parameter.

Surely learn very basic linear circuit theory before EDA Tool Play.
 

Surely understand nport.
nport can work as any of Z,Y,H,F,S matrix even if file of nport is S-parameter.

Surely learn very basic linear circuit theory before EDA Tool Play.

I am just starting to model with VerilogA, so I would need a bit of more specific advice.
The file generated from SP analysis can indeed be written as Z,Y,S parameters but how will this help?
 

I am just starting to model with VerilogA
Verilog-A has no relation at all.
Simply you are very lack of knowledge of very basic linear circuit theory.

Circuit which is substituted by nport has no direct relation to any of z,y, s.

It is no more than a linear black box.
That’s all.
 

It is no more than a linear black box.
That’s all.

I understand that it is a linear black box, but how can I cascade correctly another black box that introduces non-linearities? Or it is just not possible?
 

Simply cascade them.
Consider block diagram not verilog-A.
That’s all.

BTW, can you surely understand unidirectional model and bidirectional model ?
 
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Simply cascade them.
Consider block diagram not verilog-A.
That’s all.

BTW, can you surely understand unidirectional model and bidirectional model ?

If you mean the difference between input/output and inout ports , I think i do. But for the specific model, the ports are unidirectional.
I am thinking in terms of block diagrams :
The first block is the nport and it is cascaded with another block that clips the output according to a specified IIP3. At the final output , I want to measure the same S11,S12,S21,S22 that I measure at the output of the first block ( the nport ).
I have read about how to model nonlinear RF blocks, but on all occasions the S parameters where passed to the model as a constant value , e.g S21=5dB.
However,S21 varies over frequency and I want to include this frequency dependency.
 

You can not understand anything regarding unidirectional and bidirectional at all.

And you must not use formulation based on s-parameter, since you can not understand s-parameter.

Still you can not understand linear circuit at all.

Surely learn very basic thing before EDA Tool Play.

From all your previous posts, you have too wrong and too incomplete knowledge.
So it is very tired to teach very basic things to you.

For example, I was very tired regarding your delta sigma PLL.
https://www.edaboard.com/showthread.php?373837#6
https://www.edaboard.com/showthread.php?364412/page2#23
 

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