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    65nm bonding and pad size

    Hi everyone,

    In our lab, we are going to design with 65nm technology. I'm responsible of a team who's in charge of microelectronics integration. We'll have to bond on pad in 65nm technology and I have no idea for the pads size. We allready "wedge bonded" many and many chips with pad size around 100x80um but with 65nm I wonder what are the constraints. Wedge bonding is still suitable? Ball Bonding is necessary?

    Thanks for your reply

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    Re: 65nm bonding and pad size

    Perhaps stating the obvious now, but the pad size does not necessarily scale with the geometry per se. Pad sizes can definitely be smaller than 100x80 . Are you in control over the bonding process in your lab? If there are constraints on e.g. ball size or wedge size, why not do larger pads on the silicon?



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  3. #3
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    Re: 65nm bonding and pad size

    Quote Originally Posted by jjx View Post
    Perhaps stating the obvious now, but the pad size does not necessarily scale with the geometry per se. Pad sizes can definitely be smaller than 100x80 . Are you in control over the bonding process in your lab? If there are constraints on e.g. ball size or wedge size, why not do larger pads on the silicon?
    Generally designers make as tiny as possible the size of the pads. It's the reason why I'm looking for informations to take part of the design on this point. What I found is when the size of the pad goes down, the best way is the wedge bonding, wire diameter mini is 17um (for one supplier, I didn't look forward).



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    Re: 65nm bonding and pad size

    Bond pads are sized not only for assembly but also wafer probe. Are you going to be doing wafer level probe?



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