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Ambiguous result with Analog I/O

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big_fudge98

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Hi, I am using PVDD1ANA as my I/O with TSMC 0.18um technology. When I try to pass any signal through the I/O, it is getting attenuated quite a lot. The I/O seems to be acting as a 2 Mohm resistor in shunt with the signal path. Does anyone know where I am going wrong?
 

PVDD1ANA is a power supply pin macro, dedicated for core voltage. I doubt that it's suited for the intended purpose.
 

Can we not use that I/O for passing analog signals? If not, what I/O do we use?
 

That pad probably has some baked-in design constraints
as it's meant to be a power pad - might include clamps,
decoupling and the output is supposed to be the same
as the input only when applied a positive and fairly "stiff"
voltage source.

For analog signals that throw current, you want a pad
that's "straight through" (no series resistor) with diode
clamps appropriate to the voltage range (and maybe
their size, traded against bandwidth). For zero-current
signals like op amp inputs, use a "digital" pad for better
ESD protection (two diode "layers" w/ resistor between)
-if- you can connect them to your vdda! (or whatever
you call the "quiet" analog positive rail). If you're one of
the many trying to analog on a digital library & flow, you
may have to copy the library cell to a private library and
modify the supply connections (schematic, symbol and
layout, for verification).

I don't know this technology in any detail, but there ought
to be library documents which describe the ESD / I/O libs'
contents and show schematic cartoons, maybe even.
 

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