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The timing unchanged while every time of sythesis

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nemolee

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Dear Sir,

I think you should meet very often that the timing is changed after we sythesis our RTL code through FPGA sythesis and P & R tools. How do we prevent this condition from happening?

Thanks.
 

hi
if u change ur rtl every time bfore synthesis this is bound to happen, especially when you add combo logic.
Also ensure that you give the same options to the tool everytime, like ther P&R effort level.
 

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