Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why CTS in physical design?

Status
Not open for further replies.
D

Dan_Yang

Newbie level 5
Joined
Sep 2, 2019
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
65
Hi guys,

I am confused that why we do CTS in physical design?
The obvious purpose for CTS is to reduce CLK skew, and then fix timing violation(mainly setup). And I realized that for low-speed device, timing is easy to meet. So I wonder why we still need CTS in low speed device design.
Here are some reasons I come up with.
1. To meet the timing in different corners. Since a balanced tree is easier to meet timing requirement in all required corners.
2. To reduce power dissipation.
Even though we can fix hold through insert buffer, this means adding extra buffers compared to a well balanced tree, leading to power dissipation.

Here are my questions.
1. Whether my understanding is right?
2. Is there other reasons to do CTS?

Do looking forward for your reply!!! :)
 

Dan_Yang said:
Hi guys,

I am confused that why we do CTS in physical design?
The obvious purpose for CTS is to reduce CLK skew, and then fix timing violation(mainly setup). And I realized that for low-speed device, timing is easy to meet. So I wonder why we still need CTS in low speed device design.
Here are some reasons I come up with.
1. To meet the timing in different corners. Since a balanced tree is easier to meet timing requirement in all required corners.
2. To reduce power dissipation.
Even though we can fix hold through insert buffer, this means adding extra buffers compared to a well balanced tree, leading to power dissipation.

Here are my questions.
1. Whether my understanding is right?
2. Is there other reasons to do CTS?

Do looking forward for your reply!!! :)
Click to expand...

CTS can be "estimated" at logic synthesis with the use of a layout/flooplaning estimation flow. this is quite standard these days, supported by genus and dc.

CTS is no longer about clk skew, it hasn't been for some time now. the focus is on timing optimization concurrently with clock tree optimization.

timing is never easy to meet, even if the target frequency is super low, hold can always be an issue. you need to be super precise with CTS as not to introduce (more) hold violations. it has to be done at physical synthesis so all the wires can be extracted instead of estimated, all cells are properly placed, etc.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top