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    Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    I wrote a verilog code of a counter and after implementation in FPGA board I came to know that it can work with a clock rate of 50 MHz. Whether it is needed to set the same clock frequency in the constraint file during synthesis using Cadence Genus tool. What happen if I will increase the clock frequency to 100 MHz, during cadence genus synthesis.

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    Re: Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    Hi,

    You set the frequency according your requirement.
    If you need it to work with 50MHz, then set it to 50MHz
    If you need it to work with 100MHz, then set it to 100MHz.

    If you set it to a higher frequency than needed, then you may stress the compiler, since it now tries to find a (more difficult) solution for 100MHz.

    Klaus
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    Re: Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    Thanks KlausST
    What I got is that the ASIC will work at 100 MHz, only the compiler needed to do some more work.
    Now, My question is, is there will be any Violations like timing violations etc. if I set 100 MHz in the genus synthesis.



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    Re: Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    Hi,

    it now tries to find a (more difficult) solution for 100MHz.
    It does not necessarily mean that it finds a solution .... it just tries.

    When an ASIC is specified to run at 100MHz, then this is just for a known function. Often an n bit binary counter. (Read documentation)
    But more complex logic needs longer time for a signal to be processed from pin A to pin B.
    Thus more complex functions can not run at 100MHz.

    If you are doing bad design.... maybe it can't even run at 20MHz.

    100MHz is some kind if timing specification. As said: the compiler tries to find a solution. If it does not find a solution then the result is a timing violation shown in the compiler report.

    Thus: set the frequency and the other timing constrains to the values your application needs.

    Klaus
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    Re: Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    There is no clear rule on how to convert the max clock frequency of an FPGA implementation to an ASIC implementation. Play with the synthesis tool, try some higher values and see what you get. There can easily be a 1 order of magnitude difference.
    Really, I am not Sam.



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    Re: Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    I would say first do the analysis for ASIC impl. You will get a max clk value, above which you will have clock violations. Keep that fixed for ASIC.

    Use the same clk in your constraints file for FPGA impl. If the FPGA PnR tool reports violation, then reduce the clk to the required amount so that there are no violations and proceed with your work.

    As mentioned in the above post, play with your constraints file for both ASIC and FPGA.
    FPGA enthusiast!



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