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  1. #1
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    Problem in layout result of MOS pseudo resistor

    Dear friends,

    I am trying to design a MOS pseudo resistor to use it as an average resistor for the CMFB ampliifer rather than using the big poly resistor, I am using the one shown in the schematc becture below.

    Click image for larger version. 

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ID:	156610

    for the test I am simulating I am simulating by a DC source a differential voltage to the resistor terminal, Note that GND pin is only needed for the layout purpose to connect the P-Wafer to the ground and has nothing to do with the circuit. The simulation setup and schematic result are shown below. As you see from the result, the resistor is quite good and linear for the entire differential region.

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ID:	156611

    Click image for larger version. 

Name:	schematic_result.png 
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ID:	156612

    Afterthen I did the layout with no LVS error as shown below

    Click image for larger version. 

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ID:	156613

    Now the post layout simulation is something very diviated from the schematic one as shown below

    Click image for larger version. 

Name:	layout_result.PNG 
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ID:	156614

    I wouls expect a change from layout but not as huge as this one,
    I would appreciate your help in this manner
    thanks

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  2. #2
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    Re: Problem in layout result of MOS pseudo resistor

    It almost looks too good in the schematic ... what do net8 and net10 look like in the two modalities?



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