Puppet123
Full Member level 6
Hello,
I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre.
How can I use SystemVerilog files ? Can I use them just as I use Verilog-A or Verilog-AMS files ? Will Cadence Virtuoso/Spectre/Incisive/AMS recognize SystemVerilog and just compile and simulate just as with Verilog-A and Verilog-AMS ? Are there any special considerations in using SystemVerilog with Cadence Virtuoso/Spectre/Incisive/AMS?
Thanks.
I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre.
How can I use SystemVerilog files ? Can I use them just as I use Verilog-A or Verilog-AMS files ? Will Cadence Virtuoso/Spectre/Incisive/AMS recognize SystemVerilog and just compile and simulate just as with Verilog-A and Verilog-AMS ? Are there any special considerations in using SystemVerilog with Cadence Virtuoso/Spectre/Incisive/AMS?
Thanks.
