+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Full Member level 5
    Points: 1,732, Level: 9

    Join Date
    Apr 2017
    Posts
    262
    Helped
    6 / 6
    Points
    1,732
    Level
    9

    SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    Hello,

    I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre.

    How can I use SystemVerilog files ? Can I use them just as I use Verilog-A or Verilog-AMS files ? Will Cadence Virtuoso/Spectre/Incisive/AMS recognize SystemVerilog and just compile and simulate just as with Verilog-A and Verilog-AMS ? Are there any special considerations in using SystemVerilog with Cadence Virtuoso/Spectre/Incisive/AMS?

    Thanks.

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 17,409, Level: 31
    pancho_hideboo's Avatar
    Join Date
    Oct 2006
    Location
    Real Homeless
    Posts
    2,681
    Helped
    724 / 724
    Points
    17,409
    Level
    31

    Re: SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    https://designers-guide.org/forum/Ya...num=1574282166

    Use file name of “*.sv”.

    Surely understand basic things correctly before EDA Tool Play.
    This is very true for all your previous posts.
    Last edited by pancho_hideboo; 21st November 2019 at 01:18.



    •   AltAdvertisement

        
       

  3. #3
    Full Member level 5
    Points: 1,732, Level: 9

    Join Date
    Apr 2017
    Posts
    262
    Helped
    6 / 6
    Points
    1,732
    Level
    9

    Re: SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    I know what .sv is.

    I am talking about analog / mixed signal simulation.



--[[ ]]--