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Current Reference in Sub-Threshold region

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gokulpgk

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Hello Everyone,

I am trying to design the attached circuit to generate the temperature independent PTAT current reference.

Is it advisable to design the current mirrors in the Sub-Threshold region?

(Supply Voltage = 1.8V and Threshold voltage of transistors = 0.3V).

Current_Reference.PNG
 

Probably it is possible to operate at the edge of the threshold voltage, but deep sub-threshold is not recommended becasue of worse matching between the circuit and the output current mirror. Question is how much area you have, do you have a limit?
Stacked diodes are not too good (Mp1 and Mp2) in any design, rather use 1 diode and solve the cascode output with extra circuitry. I mean keep the output cascode device (Mp6) and generate its bias voltage with other current mirrors + PMOS diode, which mirrors aren't cascoded. It would help a lot on spare drain-source voltages and designed device Vdsat voltages could be higher.
 
Probably it is possible to operate at the edge of the threshold voltage, but deep sub-threshold is not recommended becasue of worse matching between the circuit and the output current mirror. Question is how much area you have, do you have a limit?
Stacked diodes are not too good (Mp1 and Mp2) in any design, rather use 1 diode and solve the cascode output with extra circuitry. I mean keep the output cascode device (Mp6) and generate its bias voltage with other current mirrors + PMOS diode, which mirrors aren't cascoded. It would help a lot on spare drain-source voltages and designed device Vdsat voltages could be higher.

Hi,

Thank you very much for your support.

I do not have a limit in my area but I have a limit in the power consumption.
 

Extra circuitry doesn't need big consumption, rather area. And it is more effective.
 
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