Design a system clock monitor in verilog

[bravo1234]

How can I approach to design a system clock monitor logic in verilog where same clock is used as reference in FPGA ?

[barry]

Wait, you want to monitor a clock with ITSELF? Either I don't understand your question, or you're on a fool's errand. Maybe you need to restate what you are intending to do.

[bravo1234]

Wait, you want to monitor a clock with ITSELF? Either I don't understand your question, or you're on a fool's errand. Maybe you need to restate what you are intending to do.

So basically , lets just say there is a external clock generated via crystal oscillator which is also used by the FPGA chip as reference. Now is it possible to implement a monitoring logic ,in the same FPGA, to detect the failure of the external clock from crystal oscillator?

[FvM]

Yes, using an auxiliary clock, e.g. built-in FPGA RC oscillator.

Usually a clock monitor makes only sense if you have second clock you can switch to.