ghertz
Newbie level 5
I'd like to eliminate assignment of signals to every single instantiation of the interface -- see comments [1] and [2] in topmost code snippet. What is the best way to accomplish this? One way is to assign signal to a common interface and then use this common interface to connect to the other two interfaces -- need to try this out.
Code:
module top (
input [1:0] in,
output [2:0] out
);
//wires and registers
wire [1:0] module_a_out;
wire [1:0] module_b_out;
//IO assignments
assign out = module_a_out | module_b_out;
Myinterface Myif1();
Myinterface Myif2();
//[1]interface 1 to module a -- better way to accomplish this?
assign Myif1.in = in;
assign module_a_out = Myif1.out
//[2]interface 2 to module b -- better way to accomplish this?
assign Myif2.in = in;
assign module_b_out = Myif2.out
module_a module_a (.my_if_s(Myif1));
module_b module_b (.my_if_s(Myif2));
endmodule
Code:
module module_a(Myinterface.S my_if_s);
<something1>
endmodule
Code:
module module_b(Myinterface.S my_if_s);
<something2>
endmodule
Code:
interface Myinterface;
logic [1:0] in;
logic [1:0] out;
//master
modport M(output in,input out);
modport S(input in,output out);
endinterface: Myinterface