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SystemVerilog Interface signal assignment

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ghertz

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I'd like to eliminate assignment of signals to every single instantiation of the interface -- see comments [1] and [2] in topmost code snippet. What is the best way to accomplish this? One way is to assign signal to a common interface and then use this common interface to connect to the other two interfaces -- need to try this out.

Code:
module top (
   input [1:0] in,
   output [2:0] out
);

//wires and registers
wire [1:0] module_a_out;
wire [1:0] module_b_out;

//IO assignments
assign out = module_a_out | module_b_out;

Myinterface Myif1();
Myinterface Myif2();

//[1]interface 1 to module a -- better way to accomplish this?
assign Myif1.in = in; 
assign module_a_out = Myif1.out

//[2]interface 2 to module b -- better way to accomplish this?
assign Myif2.in = in;
assign module_b_out = Myif2.out

module_a module_a (.my_if_s(Myif1));
module_b module_b (.my_if_s(Myif2));

endmodule
Code:
module module_a(Myinterface.S my_if_s);
   <something1>
endmodule
Code:
module module_b(Myinterface.S my_if_s);
   <something2>
endmodule
Code:
interface Myinterface;
   logic [1:0] in;
   logic [1:0] out;
   //master
   modport M(output in,input out);
   modport S(input in,output out);
endinterface: Myinterface
 

A quick improvement is getting rid of the intermediate assignments using

Code:
assign out = Myif1.out | Myif2.out ;


As you have discovered, interfaces work best is you can keep connections together as a single instance.
Code:
module top (
  MyInterface Myif)
);

  module_a module_a (.my_if_s(Myif));
  module_b module_b (.my_if_s(Myif));

endmodule

interface Myinterface;
   logic [1:0] in;
   wor [1:0] out;
   //master
   modport M(output in,input out);
   modport S(input in,output out);
endinterface: Myinterface

module module_a(Myinterface.S my_if_s);
   // something
   assign my_if_s.out = <expression>; // get or'ed with all drivers
endmodule
 

1. I'm trying to avoid any combination logic in the interface. I'm assuming wor would get synthesized into an OR gate.

2. What happens when a different signal from a different bus acts as a select? For example:

Code:
always_comb begin
   if(my_another_if.select == 11) begin
      myif.out = myif1.out;
   end
   else if(my_another_if.select == 10) begin
      myif.out = myif2.out;
   end
   else begin
      myif.out = 2'd9;
   end
end

I was thinking about breaking up the interface into 4 different interfaces as shown below. Should I be worried about using this technique ? I want to use this because I can eliminate assigning each and every input from top interface to multiple slave interface. I can do this because I'm separating the input and output part of the slave interface.

And, when it comes to the slave outputs (and top level slave output), I could pass it up to the top and use the above code to get my final slave output. Am I defeating the purpose of using interfaces by using it in weird ways? And there are no mod-ports in these interface definitions. Is that a bad thing? I haven't used interfaces before. I'm afraid that as the code grows, I'll have to rethink my whole approach.

Code:
//slave input
interface myif_s_i;
   logic abc;
   logic pqr;
   <no modport required>
endinterface

//slave output
interface myif_s_o;
   logic abc;
   logic pqr;
   <no modport required>
endinterface

//master input
interface myif_m_i;
   logic abc;
   logic pqr;
   <no modport required>
endinterface

//master output
interface myif_m_o;
   logic abc;
   logic pqr;
   <no modport required>
endinterface
 

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