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  1. #1
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    asynchronous D Flip flop with negative edge triggered clk,set and reset

    How can we establish an equation to calculate next states based on negative edge triggered clk,rest and set
    I am experimenting with the equation::Qn+1 = !CK&(!SB|!RB)&Qn&!D
    But is not working in a generalised manner

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  2. #2
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    Re: asynchronous D Flip flop with negative edge triggered clk,set and reset

    Can you please clarify which hardware should be represented by the equation? I'm not able to read a physical sense into it.



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  3. #3
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    Re: asynchronous D Flip flop with negative edge triggered clk,set and reset

    Your equation won't work properly without an "edge detect"
    function. It is not a combinational circuit, it's a sequential
    circuit. Although you can make a flip-flop out of logic gates,
    such implementations still depend on phase lag for the
    master/slave handoff to work properly. The equation has
    nothing for that.



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