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    How to find the operating frequency for an ASIC?

    I made a verilog code for an up counter. I synthesized it in cadence genus tool by setting the clock frequency 30 MHz. After that I made a layout in Cadence Innovus tool for the same. Now my question is, how to find at what frequency my up counter ASIC will work? In FPGA the same verilog code was working at a clock rate of 20 MHz.

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  2. #2
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    Re: How to find the operating frequency for an ASIC?

    Hi,

    The usual way is to set the timing constraint first, then the compiler should optimize it to match the specifications.

    If you first set to 30MHz ... then there is no reason for a compiler to design/optimize it for higher frequency.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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  3. #3
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    Re: How to find the operating frequency for an ASIC?

    Quote Originally Posted by daskk62 View Post
    I made a verilog code for an up counter. I synthesized it in cadence genus tool by setting the clock frequency 30 MHz. After that I made a layout in Cadence Innovus tool for the same. Now my question is, how to find at what frequency my up counter ASIC will work? In FPGA the same verilog code was working at a clock rate of 20 MHz.
    The frequency is depend on process, design margin ,.. If your FPGA board signoff @20Mhz , there are no reason you increase @30Mhz if you dont want to face with setup timing violation ,..

    Tiep Ngo



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