# Doubt in the concept of 3 phase thyristor based full wave fully controlled rectifier

1. ## Doubt in the concept of 3 phase thyristor based full wave fully controlled rectifier

Consider a 3-phase fully controlled rectifier in which the thyristors are having a non-zero holding current (say 50mA). We know that the thyristors are triggered in a sequence with a phase delay of 60 deg, and at a time only one thyristor is triggered either from the postive group or from the negative group. So my question is how do any of the thyristors latch into conduction as we are turning ON only one thyristor either from the postive group or from the negative group?

In the lectures and books, they always consider ideal thyristors with zero holding current, so that the thyristor which has been triggered can remain in ON state until the other thyristor is triggered, which means, in such case, any two thyristors will remain ON all the time and we shall get a proper output voltage. But with non-zero holding current, it doesn't happen so.

This problem doesn't occur in single phase full wave rectifiers even with the non zero latching current being considered because we turn ON two thyristors at a time, one from the postive group and other from the negative group. So the thyristors can easily latch into conduction.

Simulation Graph when Latching Current is Considered (R Load, alpha = 30 deg)
The thyristors remain ON only during the time when their respective gate voltage is high, so we get a pulsed output voltage.

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2. ## Re: Doubt in the concept of 3 phase thyristor based full wave fully controlled rectif

Hi,

There are several issues in your post/schematic.

They usually explain all you need to know.

If there still are questions please post the link to the document you refer to.

Klaus

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3. ## Re: Doubt in the concept of 3 phase thyristor based full wave fully controlled rectif

its been a while since i did power, so i'm a little rusty:

KlausST is right there are several issues (several things to discuss) in your post.

if you follow the current path through the circuit for one thyrister on, you should find no path, and therefore no current flow
no current, no latching on

what you are seeing in the VP1 trace is the thyrister turning on
your simulator is giving you the voltage between VP1 and ground, not the voltage across the load

you must turn on two thyristers at a time to get conduction
when you have conduction, you should get latch on

suggestions:
change the three negative thyrister to diodes, or turn them on all the time
look at the voltage across the load (differential probes)
you should get what you expect

and do what KlausST said

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4. ## Re: Doubt in the concept of 3 phase thyristor based full wave fully controlled rectif

Not sure if the thyristors in your schematic are real semiconductor devices or virtual switches with a logic input. In the former case, the trigger current has to be applied between gate and cathode, not gate and circuit ground.

5. ## Re: Doubt in the concept of 3 phase thyristor based full wave fully controlled rectif

The nature of the "buffers" in the schematic is unclear.

If the SCR is a GTO type then a voltage mode drive could
be responsible for the pulse-following behavior. A rectified
pulse transformer and narrow trigger pulses could be a way
to go.

Old timey SCR app notes from GE, Motorola, et al would
likely have much to offer you - they put out whole books
on SCR applications back when SCRs were the only game
in town. Still are for really really high currents (hockey
puck size).

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