dipk11
Junior Member level 2
Hi all,
I am new to system Verilog and learning to write a test bench for already existing code.
I have a master.sv file which has the code for SPI master. I have written a basic testbench
(master_tb.sv)to test the master, but to simulate the SPI bus I wanted to use a verification IP already provided by sysWip.
The VIP has an interface file and a master_spi.sv file.
How do I use it in my code?
where do I instantiate the interface, start the spi environment and the connection?
do I need to change anything in my master.sv file?
I am new to system Verilog and learning to write a test bench for already existing code.
I have a master.sv file which has the code for SPI master. I have written a basic testbench
(master_tb.sv)to test the master, but to simulate the SPI bus I wanted to use a verification IP already provided by sysWip.
The VIP has an interface file and a master_spi.sv file.
How do I use it in my code?
where do I instantiate the interface, start the spi environment and the connection?
do I need to change anything in my master.sv file?