Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

max_transition Violation

Status
Not open for further replies.
V

vyella1

Newbie level 6
Joined
Jun 15, 2018
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
146
Hello Forum,
I work on front end synthesis of the design using design compiler topographical. After synthesis, there are no timing violations. But I am seeing "max_transition" violation. Is it something which we resolve at front end or at back end?
 

Maybe neither, maybe both. max_tran violations may indicate some issue in the sdc files, may indicate issues with library characterization, may indicate poor synthesis. You have to look at it case by case.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top