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DFT parallel pattern simulation mismatch analysis

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Vignesh_J

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Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI

Kindly correct me if I am wrong in this part.
For parallel pattern simulation, the values are forced in D pin of FF's by the simulator
 

Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI

Kindly correct me if I am wrong in this part.
For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
What you should trace back is the clock , time it lanuch in the shift window and double check in your procedure

Tiep Ngo
 
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