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  1. #1
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    DFT parallel pattern simulation mismatch analysis

    Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI

    Kindly correct me if I am wrong in this part.
    For parallel pattern simulation, the values are forced in D pin of FF's by the simulator

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  2. #2
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    Re: DFT parallel pattern simulation mismatch analysis

    Quote Originally Posted by Vignesh_J View Post
    Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI

    Kindly correct me if I am wrong in this part.
    For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
    For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
    What you should trace back is the clock , time it lanuch in the shift window and double check in your procedure

    Tiep Ngo
    Last edited by Tieny; 14th November 2019 at 04:35. Reason: Wrong quote



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