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  1. #1
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    Wire bonding simulation in a low noise application

    Hello everyone,
    I am currently designing two low noise amplifiers (which will respectively operate at ~20GHz and ~38GHz) with the same foundry process (D007iH from OMMIC). The transistors come as discrete chips (roughly 400x400x100 um) without via holes, the aim is to use inductive degeneration and connect the source pads to ground thanks to two gold wires (one for each source pads). The input and output DC feed/impedance match circuits are to be designed on separate alumina circuits. My question is, does anyone know how to accurately simulate the different wire bonds surrounding the transistors (drain, gate and source pads) please ? The simulations I have done so far with circuit models show they have a great impact on stability and noise performances so I really need to have accurate models. IEEE papers, PhD thesis reports, feedbacks based on experience... any input is welcome. :)
    P.S : I am using ADS and also have access to CST and HFSS licenses (but I have more experience with CST though).

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  2. #2
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    Re: Wire bonding simulation in a low noise application

    If you are able to access CST license, use it to simulate the bond-wire.It will give you an quite accurate result.
    But bond-wire can show some deviation during manufacturing, therefore model it as a parametric component and apply a MonteCarlo simulation to predict MFG variations.



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